JAJSKC8C April   2022  – August 2023 TPSI3052-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
      4. 9.2.4 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.3 CDIV1, CDIV2 Capacitance

The CDIV1 and CDIV2 capacitances required depends on the amount of drop that can be tolerated on the VDDH rail during switching of the external load. The charge stored on the CDIV1 and CDIV2 capacitances is used to provide the current to the load during switching. During switching, charge sharing occurs and the voltage on VDDH drops. At a minimum, TI recommends that the total capacitance formed by the series combination of CDIV1 and CDIV2 be sized to be at least 30 times the total gate capacitance to be switched. This sizing results in an approximate 0.5-V drop of the VDDH supply rail that is used to supply power to the VDRV signal. Equation 1 and Equation 2 can be to used to calculate the amount of capacitance required for a specified voltage drop.

CDIV1 and CDIV2 must be of the same type and tolerance.

Equation 1. C D I V 1 = n + 1 n × Q L O A D ∆ V ,   n ≥ 3.0
Equation 2. C D I V 2 = n × C D I V 1 ,   n ≥ 3.0

where

  • n is a real number greater than or equal to 3.0.
  • CDIV1 is the external capacitance from VDDH to VDDM.
  • CDIV2 is the external capacitance from VDDM to VSSS.
  • QLOAD is the total charge of the load from VDRV to VSSS.
  • ΔV is the voltage drop on VDDH when switching the load.
Note: CDIV1 and CDIV2 represent absolute capacitances and components selected must be adjusted for tolerances and any derating necessary to achieve the required capacitances.

Larger values of ΔV can be used in the application, but excessive droop can cause the VDDH undervoltage lockout falling threshold (VVDDH_UVLO_F) to be reached and cause VDRV to be asserted low. Note that as the series combination of CDIV1 and CDIV2 capacitances increases relative to QLOAD, the VDDH supply voltage drop decreases, but the initial charging of the VDDH supply voltage during power up increases.

For this design, assuming n = 3 and ΔV≅ 0.5 V, then

Equation 3. C D I V 1 = 3 + 1 3 × 120   n C 0.5   V = 320   n F
Equation 4. C D I V 2 = 3 × 320   n F = 960   n F

For this design, CDIV1 = 330 nF and CDIV2 = 1 μF standard capacitor values were selected.