VDDP must be supplied independently by a low impedance external supply that can deliver the required power. When VDDP power is present and CE is a logic high, power transfers from the primary side to the secondary side. Setting the EN pin logic high or low asserts or deasserts VDRV, thereby enabling or disabling the external switch, respectively. Figure 8-9 shows the basic set-up required for proper operation which requires EN, VDDP, and VSSP signals. EN may be driven up to 5.5-V which is normally driven from circuitry on the same rail as VDDP. In this example, the TPSI310x-Q1 is being used to drive back-to-back MOSFETs in a common-source configuration. Driving back-to-back MOSFETs is required for AC switching applications or DC switching where reverse blocking is required. C_VDDP provides the required decoupling capacitance for the VDDP supply. C_DIV1 and C_DIV2 provide the required decoupling capacitance of the VDDH/VDDM supply rails to provide peak current to drive the external MOSFETs.

Figure 8-9 Simplified Schematic

Figure 8-10 shows the basic operation from start up to steady state conditions.

• At T1: VDDP powers up the device. FLTn, ALMn, and PGOOD are asserted low.
• At T2 and T3: TPSI310x-Q1 begins to transfer power from VDDP to the secondary side for a fixed burst period (25 μs typical), which begins to charge up the VDDH and VDDM secondary side rails. Power transfer continues as long as VDDP is present (and CE remains high). The time required to fully charge VDDH depends on several factors including the values of VDDP, C_DIV1, C_DIV2, the amount of auxiliary load drawn from VDDM, and the overall power transfer efficiency.
• At T4, T5, and T6: After four burst periods, the FLTn, ALMn, and PGOOD are released and begin to reflect their respective status. PGOOD asserts high if VDDM and VDDH are both above their UVLO thresholds, otherwise remains asserted low. FLTn and ALMn indicate the status of their comparator outputs. In this example, since FLTn_CMP and ALMn_CMP are tied to VSSS, FLTn and ALMn assert high. The status indicators are always transferred sequentially in the order of FLTn, ALMn, and PGOOD with a delay of approximately 400 ns between each indicator.
• At T7 and T8: EN is asserted high and VDRV asserts high. Note that VDRV will not assert high until VDDH and VDDM are both above their UVLO thresholds. Due to latency of the FLTn, ALMn, and PGOOD indicators, it is possible that VDRV asserts high prior to PGOOD asserting high.

Figure 8-10 TPSI310x-Q1 Typical Start-up (CE = VDDP, FLTn_CMP = 0, ALMn_CMP = 0)

Figure 8-11 shows start up sequence where VDDP, CE, and EN signals are tied together.

• At T1: VDDP powers up the device. FLTn, ALMn, and PGOOD are asserted low.
• At T2 and T3: TPSI310x-Q1 begins to transfer power from VDDP to the secondary side for a fixed burst period (25 μs typical), which begins to charge up the VDDH and VDDM secondary side rails.
• At T4: VDRV asserts high when both VDDH and VDDM are above their UVLO thresholds.
• At T5, T6, and T7: After four burst periods, the FLTn, ALMn, and PGOOD are released and begin to reflect their respective status. In this specific example, it is assumed that VDDH and VDDM rails have charged up beyond their UVLO thresholds under the four burst periods (100 μs). In this case, due to the PGOOD latency, PGOOD is asserted high after VDRV is asserted high.

Figure 8-11 TPSI310x-Q1 Typical Start-up (CE = EN = VDDP, FLTn_CMP = 0, ALMn_CMP = 0)

To reduce average power, the TPSI310x-Q1 transfers power from the primary side to the secondary side in a burst fashion. The period of the burst is fixed while the burst on time is determined internally by the control loop regulating the VDDM voltage. The burst on time is automatically adjusted based upon the status of the VDDM voltage thereby optimizing power transfer for a given load condition. During power up, the device operates at the highest power setting. This helps to quickly charge up the VDDM and VDDH rails.