JAJSL38 December   2023 TPSI3100-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Over-current Fault Error
        5. 9.2.2.5 Over-current Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DVX|16
サーマルパッド・メカニカル・データ
発注情報

9.2.2.1 CDIV1, CDIV2 Capacitance

The CDIV1 and CDIV2 capacitors required depends on the amount of drop that can be tolerated on the VDDH rail during switching of the external load. The charge stored on the CDIV1 and CDIV2 capacitors is used to provide the current to the load during switching. During switching, charge sharing occurs and the voltage on VDDH drops. At a minimum, TI recommends that the total capacitance formed by the series combination of CDIV1 and CDIV2 be sized to be at least 30 times the total gate capacitance to be switched. This sizing results in an approximate 0.5-V drop of the VDDH supply rail that is used to supply power to the VDRV signal. Equation 2 and Equation 3 can be to used to calculate the amount of capacitance required for a specified voltage drop.

CDIV1 and CDIV2 must be of the same type and tolerance.

Equation 2. C D I V 1 = n + 1 n × Q L O A D ∆ V ,   n ≥ 3.0
Equation 3. C D I V 2 = n × C D I V 1 ,   n ≥ 3.0

where

  • n is a real number greater than or equal to 3.0.
  • CDIV1 is the external capacitor from VDDH to VDDM.
  • CDIV2 is the external capacitor from VDDM to VSSS.
  • QLOAD is the total charge of the load from VDRV to VSSS.
  • ΔV is the voltage drop on VDDH when switching the load.
Note: CDIV1 and CDIV2 represent absolute capacitor and components selected must be adjusted for tolerances and any derating necessary to achieve the required capacitance.

Larger values of ΔV can be used in the application, but excessive droop can cause the VDDH under-voltage lockout falling threshold (VVDDH_UVLO_F) to be reached and cause VDRV to be asserted low. Note that as the series combination of CDIV1 and CDIV2 capacitance increases relative to QLOAD, the VDDH supply voltage drop decreases, but the initial charging of the VDDH supply voltage during power up increases.

For this design, assuming n = 3 and ΔV = 0.5 V, then

Equation 4. C D I V 1 = 3 + 1 3 × 120   n C 0.5   V = 320   n F
Equation 5. C D I V 2 = 3 × 320   n F = 960   n F