Figure 9-2 Over-current protection
typical timing and behavior
At t0: VDRV is
asserted high and the external FETs are supplying load current,
ILOAD. ILOAD is in its normal operating range and is below
the alarm level setting of 5 A, nominal. ALM1_CMP and FLT1_CMP comparator input
voltages are below the comparator threshold set by VREF of the TPSI3100-Q1 of 0.3 V,nominal).
ALM1 and FLT1 faults are asserted
high pulled-up by external resistor pull-ups to VDDP.
At t1:
ILOAD current increases and reaches the alarm level setting of 5
A, nominal. ALM1_CMP comparator input voltage reaches its threshold of 0.3 V and
ALM1 asserts low within tALM_LATENCY. VDRV
remains asserted high since the FLT1_CMP comparator input threshold has not been
reached. FLT1 remains asserted high pulled-up by the
external resistor pull-up to VDDP.
At t2:
ILOAD current continues to increases and reaches the fault level
setting of 10 A, nominal. FLT1_CMP comparator input voltage reaches its
threshold of 0.3 V and VDRV is quickly asserted low to disable the external
FETs. FLT1 asserts low within tFLT_LATENCY.
ALM1 remains asserted low since the ALM1_CMP comparator
input exceeds its threshold.
At t3: Since the FETs
have been turned off, ILOAD, is removed. FLT1_CMP and ALM1_CMP
comparator inputs drop below their thresholds, settling to VSSS. VDRV remains
asserted low keeping the external FETs off for tREC_VDRV.
FLT1 and ALM1 assert high within
tFLT_LATENCY and tALM_LATENCY, respectively indicating
to the system that fault and alarm conditions have been removed.
At t4: VDRV asserts
high again since EN remains high, tREC_VDRV time has elapsed, and the
fault condition is no longer present. The external FETs are enabled and supply
ILOAD in its normal operating range.