JAJSL38 December   2023 TPSI3100-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Over-current Fault Error
        5. 9.2.2.5 Over-current Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DVX|16
サーマルパッド・メカニカル・データ
発注情報

6.9 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25 ℃. CVDDP = 1 µF, CDIV1 = 47 nF, CDIV2 = 220 nF,  CVDRV = 1 nF, IAUX = 0 mA. 50 kΩ pull-ups from FLT1, ALM1, PGOOD to VDDP. RRESP = 100 kΩ to VSSS.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON
CMTI Common-mode transient immunity, static. |VCM| = 1000 V,
VEN = 0 V or VEN = 5 V.		 100 V/ns
TSD Temperature shutdown VVDDP = 5 V 173 ℃
TSDH Temperature shutdown hysteresis VVDDP = 5 V 32 ℃
SUPPLY
IVDDP_STBY VDDP current in standby VVDDP = 5 V,
EN = 0 V,
CE = 0 V.
Measure average current.		 30 40 µA
IVDDP_LOW VDDP average current in steady state VVDDP = 5 V, EN = CE = 5 V.
Fault and alarm inputs tied to VSSP (device specific).
IAUX = 0 mA.
Lowest power regulation.
VVDDH in steady state,
measure IVDDP.		 5.3 mA
IVDDP_HIGH VDDP average current in steady state VVDDP = 5 V, EN = CE = 5 V.
Fault and alarm inputs tied to VSSS (device specific).

Highest power regulation.
VVDDH in steady state,
measure IVDDP.		 35 mA
VVDDH VDDH output voltage VVDDP = 5 V, EN = CE = 5 V.
Fault and alarm inputs tied to VSSS (device specific).		 14.7 15.8 17.1 V
VVDDM Average VDDM voltage when not sourcing current. VVDDP = 5 V, EN = CE = 5 V.
Fault and alarm inputs tied to VSSS (device specific).
 		 4.8 5.0 5.2 V
IVDDH_STBY Average standby current of VDDH supply. VVDDP = 5 V, EN = 0 V, CE = 5 V.
Fault and alarm inputs tied to VSSS (device specific).
 		 48 µA
IVDDM_STBY Average standby current of VDDM supply. VVDDP = 5 V, EN = 0 V, CE = 5 V.
Fault and alarm inputs tied to VSSS (device specific).		 115 µA
VVDDM_IAUX Average VDDM voltage when sourcing external current. VVDDP = 5 V, EN = 0 V, steady state.
Fault and alarm inputs tied to VSSS (device specific).
Source IAUX = 5 mA from VDDM, measure VVDDM.
CDIV2 = 1 µF		 4.7 5.5 V
SUPERVISORY
VVDDP_UV_R VDDP under-voltage threshold rising VDDP rising.
 		 3.9 4.1 4.35 V
VVDDP_UV_F VDDP under-voltage threshold falling
VDDP falling
 		 3.8 3.9 4.25 V
VVDDP_UV_HYS VDDP under-voltage threshold hysteresis 170 mV
VVDDH_UV_R VDDH under-voltage threshold rising VDDH rising. 12.4 13 13.5 V
VVDDH_UV_F VDDH under-voltage threshold falling.
 		 VDDH falling. 9.9 10.4 10.9 V
VVDDH_UV_HYS VDDH under-voltage threshold hysteresis.
 		 2.5 V
VVDDM_UV_R VDDM under-voltage threshold rising VDDM rising. 3.4 3.7 3.9 V
VVDDM_UV_F VDDM under-voltage threshold falling.
 		 VDDM falling. 3.1 3.4 3.7 V
VVDDM_UV_HYS VDDM under-voltage threshold hysteresis.
 		 0.3 V
DRIVER
VVDRV_H VDRV output voltage driven high VVDDP = 5 V, EN = 5 V.
VVDDH in steady state, no DC loading.
Fault and alarm inputs tied to VSSS (device specific).
 		 14.7 15.8 17.1 V
VVDRV_L VDRV output voltage driven low VVDDP = 5 V, EN = 0 V,
VVDDH in steady state,
VDRV sinking 10 mA.
Fault and alarm inputs tied to VSSS (device specific).		 0.1 V
IVDRV_PEAK VDRV peak output current during rise VVDDP = 5 V,
EN = 0 V → 5 V,
VVDDH in steady state,
measure peak current.
Fault and alarm inputs tied to VSSS (device specific).
 1.5 A
VDRV peak output current during fall VVDDP = 5 V,
EN = 5 V → 0 V,
VVDDH in steady state,
measure peak current.
Fault and alarm inputs tied to VSSS (device specific).
 2.5 A
RDSON_VDRV Driver on resistance in low state. Force VVDDH = 15 V,
sink IVDRV = 50 mA.
Fault and alarm inputs tied to VSSS (device specific).		 1.8 Ω
Driver on resistance in high state. Force VVDDH = 15 V,
source IVDRV = 50 mA.
Fault and alarm inputs tied to VSSS (device specific).		 3.6 Ω
DIGITAL INPUT/OUTPUT
VIT_+(EN) Input threshold voltage
rising on EN.		 VVDDP = 5 V 2.2 2.4 2.6 V
VIT_-(EN) Input threshold voltage
falling on EN.		 VVDDP = 5 V 1.7 1.9 2.0 V
VIT_HYS(EN) Input threshold voltage
hysteresis on EN.		 VVDDP = 5 V 0.5 V
VIT_+(CE) Input threshold voltage
rising on CE.		 VVDDP = 5 V 2.2 2.4 2.6 V
VIT_-(CE) Input threshold voltage
falling on CE.		 VVDDP = 5 V 1.7 1.9 2.0 V
VIT_HYS(CE) Input threshold voltage
hysteresis on CE.		 VVDDP = 5 V 0.5 V
VOL Low level output voltage.
PGOOD
FLT1 (TPSI310x, TPSI312x, TPSI313x)
FLT2 (TPSI312x)
ALM1 (TPSI310x, TPSI311x, TPSI313x)
ALM2 (TPSI311x)		 VVDDP = 4.5 V to 5.5 V,
IOL = 2 mA.
Outputs enabled.		 0.4 V
IOL Low level output current.
PGOOD
FLT1 (TPSI310x, TPSI312x, TPSI313x)
FLT2 (TPSI312x)
ALM1 (TPSI310x, TPSI311x, TPSI313x)
ALM2 (TPSI311x)		 VVDDP = 4.5 V to 5.5 V,
VOL = 0.4 V.
Outputs enabled.		 -2 mA
VOL_FLT_CMP Open-drain output,
low level output voltage.
FLT_CMP1 (TPSI313x)		 VVDDP = 4.5 V to 5.5 V,
IOL = 2 mA,
CE = 1, EN = 0.		 0.1 V
IOL_FLT_CMP Open-drain output,
low level output current.
FLT_CMP1 (TPSI313x)		 VVDDP = 4.5 V to 5.5 V,
VOL = 0.4 V,
CE = 1, EN = 0.		 -2 mA
ILKG Leakage current.
PGOOD
FLT1 (TPSI310x, TPSI312x, TPSI313x)
FLT2 (TPSI312x)
ALM1 (TPSI310x, TPSI311x, TPSI313x)
ALM2 (TPSI311x)		 VVDDP = 4.5 V to 5.5 V,
Outputs disabled.		 2 µA
REN_PULLDOWN Internal resistor pull-down on EN. VVDDP = 5 V 400 500 600 kΩ
RCE_PULLDOWN Internal resistor pull-down on CE. VVDDP = 5 V 400 500 600 kΩ
REFERENCE
VREF Internal reference voltage.
TPSI3100, TPSI3110, TPSI3120, TPSI3130 devices.
 
TA = 25°C		 0.31 V
Internal reference voltage.
TPSI3103, TPSI3113, TPSI3123, TPSI3133 devices.
 
TA = 25°C		 1.2 V
VREF_TOL Internal reference voltage tolerance. -1.5 1.5 %
COMPARATORS
RCMP_PULLDOWN Internal resistor pull-down.
FLT1_CMP, ALM1_CMP (TPSI310x, TPS313x)
FLT1_CMP, FLT2_CMP (TPSI311x)
ALM1_CMP. ALM1_CMP (TPSI312x)		 1.9 3 3.6 MΩ