JAJSPL6A October   2023  – December 2023 TPSM365R1 , TPSM365R15

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Shutdown, and Start-Up
      2. 7.3.2  External CLK SYNC (With MODE/SYNC)
        1. 7.3.2.1 Pulse Dependent MODE/SYNC Pin Control
      3. 7.3.3  Adjustable Switching Frequency (with RT)
      4. 7.3.4  Power-Good Output Operation
      5. 7.3.5  Internal LDO, VCC UVLO, and VOUT/FB Input
      6. 7.3.6  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      7. 7.3.7  Output Voltage Selection
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Soft Start and Recovery from Dropout
        1. 7.3.9.1 Soft Start
        2. 7.3.9.2 Recovery from Dropout
      10. 7.3.10 Current Limit and Short Circuit
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode - Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode - Light Load Operation
        4. 7.4.3.4 Minimum On-time Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Choosing the Switching Frequency
        3. 8.2.2.3  Setting the Output Voltage
        4. 8.2.2.4  Input Capacitor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  VCC
        7. 8.2.2.7  CFF Selection
        8. 8.2.2.8  External UVLO
        9. 8.2.2.9  Power-Good Signal
        10. 8.2.2.10 Maximum Ambient Temperature
        11. 8.2.2.11 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

The TPSM365R1x is an easy-to-use, synchronous buck, DC/DC power module that operates from a 3-V to 65-V supply voltage. With an integrated power controller, inductor, and MOSFETs, the TPSM365R1x delivers up to 150-mA or 100-mA DC load current with high efficiency and ultra-low input quiescent current in a very compact design size. The TPSM365R1x can operate over a wide range of switching frequencies and duty ratios. If the minimum ON-time or OFF-time cannot support the desired duty ratio, the switching frequency is reduced automatically, maintaining the output voltage regulation. Although designed for simple implementation, this device offers flexibility to optimize the usage according to the target application.

The TPSM365R1x module also includes inherent protection features for robust system requirements:

  • An open-drain PGOOD indicator for power-rail sequencing and fault reporting
  • Precision enable input with hysteresis, providing:
    • Programmable line undervoltage lockout (UVLO)
    • Remote ON and OFF capability
  • Internally fixed output-voltage soft start with monotonic start-up into prebiased loads
  • Current limiting implemented by cycle-by-cycle peak and valley current limits
  • Thermal shutdown with automatic recovery

These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for a simple layout, requiring few external components. See Layout for a layout example.

The TPSM365R1x incorporates specific features to improve EMI performance in noise-sensitive applications:

  • An optimized package that incorporates flip chip on lead (FCOL) technology and pinout design which enables a shielded switch-node layout that mitigates radiated EMI
  • A programmable switching frequency from 200 kHz to 2.2 MHz enables optimization of external passives and promotes the avoidance of noise sensitive bands
  • Pseudo-Random Spread Spectrum (PRSS) modulation reduces peak emissions
  • Clock synchronization via the MODE/SYNC pin and FPWM mode enable constant switching frequency across the load current range
Together, these features reduce the need for any common-mode choke, shielding, and input filter inductor, greatly reducing the complexities and cost of the EMI/EMC mitigation measures.