JAJSPL6A October   2023  – December 2023 TPSM365R1 , TPSM365R15

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Shutdown, and Start-Up
      2. 7.3.2  External CLK SYNC (With MODE/SYNC)
        1. 7.3.2.1 Pulse Dependent MODE/SYNC Pin Control
      3. 7.3.3  Adjustable Switching Frequency (with RT)
      4. 7.3.4  Power-Good Output Operation
      5. 7.3.5  Internal LDO, VCC UVLO, and VOUT/FB Input
      6. 7.3.6  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      7. 7.3.7  Output Voltage Selection
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Soft Start and Recovery from Dropout
        1. 7.3.9.1 Soft Start
        2. 7.3.9.2 Recovery from Dropout
      10. 7.3.10 Current Limit and Short Circuit
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode - Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode - Light Load Operation
        4. 7.4.3.4 Minimum On-time Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Choosing the Switching Frequency
        3. 8.2.2.3  Setting the Output Voltage
        4. 8.2.2.4  Input Capacitor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  VCC
        7. 8.2.2.7  CFF Selection
        8. 8.2.2.8  External UVLO
        9. 8.2.2.9  Power-Good Signal
        10. 8.2.2.10 Maximum Ambient Temperature
        11. 8.2.2.11 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1 Enable, Shutdown, and Start-Up

The voltage at the EN/UVLO pin controls the startup voltage and shut-down voltage of the TPSM365R1x. There are three distinct modes set by the EN/UVLO pin; shutdown, standby, and active. As long as the EN/UVLO pin voltage is less than VEN-WAKE the device is shutdown mode. During shutdown mode, the input current drawn by the device typically is 0.55 µA (VIN = 13.5 V). The internal LDO regulator is not operational. When the voltage at the EN/UVLO pin is greater than the VEN-WAKE but less than VEN-VOUT the device enters the standby mode. In standby mode the internal LDO is enabled. As the EN/UVLO pin voltage increases above VEN-VOUT, the device enters active mode starting the feedback resistor detection. After feedback detect is completed, soft-start functionality is released to slowly increases the output voltage and switching starts. To stop switching and enter standby mode the EN/UVLO pin must fall below (VEN-VOUT – VEN-HYST). Any further decrease in the EN/UVLO pin voltage below VEN-WAKE the device is in shutdown. The various EN/UVLO threshold parameters and their values are listed in Section 6.5. See Section 7.3.7 for information about feedback resistor detection. Figure 7-1 shows the precision enable behavior.

GUID-20231010-SS0I-NNLG-43TQ-ZPSWP8WRQG5D-low.svg Figure 7-1 Precision Enable Behavior

Remote precision undervoltage lockout can be implemented with this functionality as shown in Figure 7-2. See Section 8.2.2.8 for component selection.

GUID-D9C6F106-4C17-4996-8111-12C4E3DA46A3-low.gifFigure 7-2 VIN Undervoltage Lockout
Using the EN/UVLO Pin

The high-voltage compliant EN/UVLO pin can be connected directly to the VIN input pin if remote precision control is not needed. The EN/UVLO pin must not be allowed to float. The various EN threshold parameters are listed in the Section 6.5. Figure 7-1 shows the precision enable behavior. After EN/UVLO goes above VEN-VOUT with a delay of about 1 ms, the output voltage begins to rise with a soft-start and reaches close to the final value in about 2.58 ms (tss). After a delay of about 2 ms (tPGOOD_ACT), the PGOOD flag goes high. During startup, the device is not allowed to enter FPWM mode until the soft-start time has elapsed. Check Section 8.2.2.8 for component selection.