JAJSNY9B September   2022  – February 2023 TPSM365R3 , TPSM365R6

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  System Characteristics
    7. 8.7  Typical Characteristics
    8. 8.8  Typical Characteristics: VIN = 12 V
    9. 8.9  Typical Characteristics: VIN = 24 V
    10. 8.10 Typical Characteristics: VIN = 48 V
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Input Voltage Range
      2. 9.3.2  Output Voltage Selection
      3. 9.3.3  Input Capacitors
      4. 9.3.4  Output Capacitors
      5. 9.3.5  Enable, Start-Up, and Shutdown
      6. 9.3.6  External CLK SYNC (with MODE/SYNC)
        1. 9.3.6.1 Pulse-Dependent MODE/SYNC Pin Control
      7. 9.3.7  Switching Frequency (RT)
      8. 9.3.8  Power-Good Output Operation
      9. 9.3.9  Internal LDO, VCC UVLO, and BIAS Input
      10. 9.3.10 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      11. 9.3.11 Spread Spectrum
      12. 9.3.12 Soft Start and Recovery from Dropout
        1. 9.3.12.1 Recovery from Dropout
      13. 9.3.13 Overcurrent Protection (OCP)
      14. 9.3.14 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Active Mode
        1. 9.4.3.1 CCM Mode
        2. 9.4.3.2 AUTO Mode - Light Load Operation
          1. 9.4.3.2.1 Diode Emulation
          2. 9.4.3.2.2 Frequency Reduction
        3. 9.4.3.3 FPWM Mode - Light Load Operation
        4. 9.4.3.4 Minimum On-time (High Input Voltage) Operation
      4. 9.4.4 Dropout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 600-mA and 300-mA Synchronous Buck Regulator for Industrial Applications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 10.2.1.2.2  Output Voltage Setpoint
          3. 10.2.1.2.3  Switching Frequency Selection
          4. 10.2.1.2.4  Input Capacitor Selection
          5. 10.2.1.2.5  Output Capacitor Selection
          6. 10.2.1.2.6  VCC
          7. 10.2.1.2.7  CFF Selection
          8. 10.2.1.2.8  Power-Good Signal
          9. 10.2.1.2.9  Maximum Ambient Temperature
          10. 10.2.1.2.10 Other Connections
        3. 10.2.1.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Ground and Thermal Considerations
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Development Support
        1. 11.1.3.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.10 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)

The high-side switch driver circuit requires a bias voltage higher than VIN to ensure the HS switch is turned ON. There is an internal 0.1-μF capacitor connected between BOOT and SW that operates as a charge pump to boost the voltage on the BOOT terminal to (SW + VCC). The boot diode is integrated on the TPSM365Rx die to minimize physical solution size. The BOOT rail has an UVLO setting. This UVLO has a threshold of VBOOT-UVLO and is typically set at 2.3 V. If the BOOT capacitor is not charged above this voltage with respect to the SW pin, then the part initiates a charging sequence, turning on the low-side switch before attempting to turn on the high-side device.