JAJSNY9B September 2022 – February 2023 TPSM365R3 , TPSM365R6
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY VOLTAGE (VIN PIN) | ||||||
VIN_R | Minimum operating Input Voltage (Rising) | Rising Threshold | 3.4 | 3.6 | V | |
VIN_F | Minimum operating Input Voltage (Falling) | Once Operating; Falling Threshold | 2.45 | 3.0 | V | |
IQ_13p5_Fixed | Non-switching input current; measured at VIN pin (2) | VIN = VEN = 13.5 V; VBIAS = 5.25 V, VMODE/SYNC = 0 V; Fixed Output Option | 0.25 | 0.672 | 1.05 | µA |
IQ_13p5_Adj | Non-switching input current; measured at VIN pin (2) | VIN = VEN = 13.5 V; VFB = 1.5 V, VRT = 0 V; Adjustable Output Option | 11 | 17 | 24 | µA |
IQ_24p0_Fixed | Non-switching input current; measured at VIN pin (2) | VIN = VEN = 24 V; VBIAS = 5.25 V, VMODE/SYNC = 0 V; Fixed Output Option | 0.8 | 1.2 | 1.7 | µA |
IQ_24p0_Adj | Non-switching input current; measured at VIN pin (2) | VIN = VEN = 24 V; VFB = 1.5 V, VRT = 0 V; Adjustable Output Option | 11 | 18 | 24 | µA |
IB_13p5 | Current into BIAS pin (not switching) (3) | VIN = VEN = 13.5 V, VBIAS = 5.25 V, VMODE/SYNC = 0 V; Fixed Output Option | 14 | 17 | 22 | µA |
IB_24p0 | Current into BIAS pin (not switching) (3) | VIN = VEN = 24 V, VBIAS = 5.25 V, VMODE/SYNC = 0 V; Fixed Output Option | 14 | 18 | 22 | µA |
ISD_13p5 | Shutdown quiescent current; measured at VIN pin (2) | VEN = 0 V; VIN = 13.5 V | 0.5 | 1.3 | µA | |
ISD_24p0 | Shutdown quiescent current; measured at VIN pin (2) | VEN = 0 V; VIN = 24 V | 1 | 1.8 | µA | |
ENABLE (EN PIN) | ||||||
VEN-WAKE | Enable wake-up threshold | 0.4 | V | |||
VEN-VOUT | Precision enable high level for VOUT | 1.16 | 1.263 | 1.36 | V | |
VEN-HYST | Enable threshold hysteresis below VEN-VOUT | 0.3 | 0.35 | 0.4 | V | |
ILKG-EN | Enable input leakage current | VEN = 3.3 V | 0.3 | 10 | nA | |
INTERNAL LDO | ||||||
VCC | Internal VCC voltage | Adjustable or Fixed Output Option; Auto mode | 3.125 | 3.15 | 3.22 | V |
ICC | Bias regulator current limit | 65 | 240 | mA | ||
VCC-UVLO | Internal VCC undervoltage lockout | VCC rising under voltage threshold | 3 | 3.3 | 3.65 | V |
VCC-UVLO-HYST | Internal VCC under voltage lock-out hysteresis | Hysteresis below VCC-UVLO | 0.4 | 0.8 | 1.2 | V |
CURRENT LIMITS | ||||||
ISC-0p3 | Short circuit high side current limit (2) | 0.3 A version (TPSM365R3) | 0.42 | 0.5 | 0.575 | A |
ILS-LIMIT-0p3 | Low side current limit (2) | 0.3 A version (TPSM365R3) | 0.27 | 0.35 | 0.42 | A |
IPEAK-MIN-0p3 | Minimum Peak Inductor Current (2) | Auto operation, 0.3 A version; Duty Cycle = 0%; (TPSM365R3) | 0.065 | 0.09 | 0.113 | A |
ISC-0p6 | Short circuit high side current limit (2) | 0.6 A version (TPSM365R6) | 0.87 | 1 | 1.11 | A |
ILS-LIMIT-0p6 | Low side current limit (2) | 0.6 A version (TPSM365R6) | 0.6 | 0.7 | 0.8 | A |
IPEAK-MIN-0p6 | Minimum Peak Inductor Current (2) | Auto operation, 0.6 A version; Duty Cycle = 0%; (TPSM365R6) | 0.127 | 0.19 | 0.227 | A |
IZC | Zero Cross Current (2) | Auto mode operation; (TPSM365R3) and (TPSM365R6) | 0.01 | 0.025 | A | |
IL-NEG | Negative current limit (2) | FPWM operation; (TPSM365R3) and (TPSM365R6) | –0.8 | –0.7 | –0.6 | A |
POWER GOOD | ||||||
VPG-OV | PGOOD upper threshold - Rising | % of BIAS or FB (adjustable or fixed output) | 106 | 107 | 110 | % |
VPG-UV | PGOOD lower threshold - Falling | % of BIAS or FB (adjustable or fixed output) | 93 | 94 | 96.5 | % |
VPG-HYS | PGOOD hysteresis | % of BIAS or FB (adjustable or fixed output) | 1.3 | 1.8 | 2.3 | % |
VPG-VALID | Minimum input voltage for proper PGOOD function | 0.72 | 1 | 2 | V | |
RPG-EN5p0 | RDS(ON) PGOOD output | VEN = 5 V, 1 mA pull-up current | 20 | 40 | 70 | Ω |
RPG-EN0 | RDS(ON) PGOOD output | VEN = 0 V, 1 mA pull-up current | 10 | 18 | 31 | Ω |
tRESET_FILTER | PGOOD deglitch delay at falling edge | 15 | 25 | 40 | µs | |
tPGOOD_ACT | Delay time to PGOOD high signal | 1.7 | 1.956 | 2.16 | ms | |
SOFT START | ||||||
tSS | Time from first SW pulse to VOUT/FB at 90% of set point | 1.95 | 2.58 | 3.2 | ms | |
OSCILLATOR (MODE/SYNC) | ||||||
VSYNC-H | SYNC input and mode high level threshold | 1.8 | V | |||
VSYNC-L | SYNC input and mode low level threshold | 0.8 | V | |||
VSYNC-HYS | SYNC input hysteresis | 230 | 300 | 380 | mV | |
tPULSE_H | High duration needed to be recognized as a pulse | 100 | ns | |||
tPULSE_L | Low duration needed to be recognized as a pulse | 100 | ns | |||
tSYNC | High/Low signal duration to be recognized as a valid synchronization signal | 6 | 9 | 12 | µs | |
tMODE | Time at one level needed to indicate FPWM or Auto Mode | 18 | µs | |||
OSCILLATOR (RT) | ||||||
fOSC_2p2MHz | Internal oscillator frequency | RT = GND | 2.1 | 2.2 | 2.3 | MHz |
fOSC_1p0MHz | Internal oscillator frequency | RT = VCC | 0.93 | 1 | 1.05 | MHz |
fADJ_400kHz | RT = 39.2 kΩ (with RT variant only) | 0.34 | 0.4 | 0.46 | MHz | |
SWITCH NODE (SW) | ||||||
tON-MIN | Minimum switch on-time | VIN = 24 V, IOUT = 0.6 A | 40 | 57 | 86 | ns |
tOFF-MIN | Minimum switch off-time | 40 | 58 | 77 | ns | |
tON-MAX | Maximum switch on-time | High-side timeout in dropout | 7.6 | 9 | 9.8 | µs |
MOSFETS | ||||||
RDSON-HS | High-side MOSFET on-resistance | Load = 0.3 A | 560 | 920 | mΩ | |
RDSON-LS | Low-side MOSFET on-resistance | Load = 0.3 A | 280 | 480 | mΩ | |
VBOOT-UVLO | BOOT - SW UVLO threshold (3) | 2.14 | 2.3 | 2.42 | V | |
VOLTAGE REFERENCE | ||||||
VOUT_Fixed3p3 | Initial VOUT voltage accuracy for 3.3-V | 3.3-V VOUT; VIN = 3.6 V to 65 V; FPWM Mode | 3.25 | 3.3 | 3.34 | V |
VOUT_Fixed5p0 | Initial VOUT voltage accuracy for 5-V | 5-V VOUT; VIN = 5.5 V to 65 V; FPWM Mode | 4.93 | 5 | 5.07 | V |
VFB | Internal reference voltage accuracy | VIN = 3.6 V to 65 V; FPWM Mode | 0.985 | 1 | 1.01 | V |
IFB | FB input current | Adjsutable output, FB = 1 V | 85 | 115 | nA |