JAJSKO8B December   2020  – October 2021 TPSM5601R5H , TPSM5601R5HE

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics (VIN = 12 V)
    7. 7.7 Typical Characteristics (VIN = 24 V)
    8. 7.8 Typical Characteristics (VIN = 48 V)
    9. 7.9 Typical Characteristics (VIN = 60 V)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Output Voltage (FB)
      2. 8.3.2 Minimum Input Capacitance
      3. 8.3.3 Minimum Output Capacitance
      4. 8.3.4 Precision Enable (EN), Undervoltage Lockout (UVLO), and Hysteresis (HYS)
      5. 8.3.5 Power Good (PGOOD)
      6. 8.3.6 Spread Spectrum Operation
      7. 8.3.7 Overcurrent Protection (OCP)
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Shutdown Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Output Voltage Setpoint
        3. 9.2.2.3 Input Capacitors
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Power Good Signal
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Theta JA versus PCB Area
      2. 11.2.2 Package Specifications
      3. 11.2.3 EMI
        1. 11.2.3.1 EMI Plots
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 11-1 and Figure 11-2 show a typical PCB layout. Some considerations for an optimized layout are:

  • Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
  • Connect all PGND pins together using copper plane.
  • Connect AGND pin to the PGND copper at a single point near the pin.
  • Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
  • Locate additional output capacitors between the ceramic capacitor and the load.
  • Place RFBT and RFBB as close as possible to their respective pins.
  • Use multiple vias to connect the power planes to internal layers.