JAJSEZ8A July   2017  – March 2018 TPSM82480

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図 space
      2.      効率と出力電流との関係 space space
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable / Shutdown (EN)
      2. 7.3.2  Soft Start (SS), Pre-biased Output
      3. 7.3.3  Tracking (TR)
      4. 7.3.4  Output Voltage Select (VSEL)
      5. 7.3.5  Forced PWM (MODE)
      6. 7.3.6  Power Good (PG)
      7. 7.3.7  Thermal Good (TG)
      8. 7.3.8  Active Output Discharge
      9. 7.3.9  Undervoltage Lockout (UVLO)
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Width Modulation (PWM) Operation
      2. 7.4.2 Power Save Mode (PSM) Operation
      3. 7.4.3 Minimum Duty Cycle and 100% Mode Operation
      4. 7.4.4 Phase Shifted Operation
      5. 7.4.5 Phase Add/Shed and Current Balancing
      6. 7.4.6 Current Limit and Short Circuit Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Adjustable Output Voltage
        2. 8.2.2.2 Setting VOUT2 Using the VSEL Feature
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Soft Start Capacitor Selection
        6. 8.2.2.6 Tracking
        7. 8.2.2.7 Thermal Good
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to 125°C) and VIN = 2.4 V to 5.5 V. Typical values at VIN = 3.6 V and TJ = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input Voltage Range VIN rising 2.6 5.5 V
VIN falling 2.4 5.5
IQ Operating Quiescent Current EN = High, VIN ≥ 3 V, IOUT = 0 mA, device not switching,
TJ = -40°C to +85°C		 23 38 µA
100% Mode operation 3.5 6.5 mA
ISD Shutdown Current EN = Low (≤ 0.3 V), TJ = -40°C to +85°C 0.5 18.5 µA
VUVLO Undervoltage Lockout Threshold Falling Input Voltage 2.2 2.3 2.4 V
Hysteresis 200 mV
TSD Thermal Shutdown Temperature PWM Mode, Rising Junction Temperature 160 °C
Thermal Shutdown Hysteresis PWM Mode 10
CONTROL (EN, VSEL, MODE, SS/TR, PG, TG)
VH Input Threshold Voltage (EN, VSEL, MODE) to ensure High Level 1.2 V
VL Input Threshold Voltage (EN, VSEL, MODE) to ensure Low Level 0.4
ILKG(EN) Input Leakage Current (EN) EN = VIN or GND 10 200 nA
ILKG(MODE) Input Leakage Current (MODE, VSEL) 10 200 nA
ISS/TR SS/TR pin source current 4.7 5.25 5.8 µA
VTH(TG) Thermal Good Threshold Temperature PWM Mode 120 °C
Thermal Good Hysteresis PWM Mode 10
VTH(PG) Power Good Threshold Voltage Rising (%VOUT) 93% 96% 99%
Falling (%VOUT) 89% 92% 95%
VL(PG) Output Low Threshold (PG, TG) IPG = -2 mA 0.4 V
ILKG(PG) Input Leakage Current (PG) 2 700 nA
ILKG(TG) Input Leakage Current (TG) 2 100 nA
tSS Internal Soft-Start Time SS/TR = VIN or floating 80 µs
tDELAY Time from EN rising until start switching 100 200 400 µs
POWER SWITCH
RDS(ON) High-Side MOSFET
ON-Resistance		 VIN ≥ 3 V Phase1 36 98 mΩ
Phase2
Low-Side MOSFET
ON-Resistance		 Phase1 29 72 mΩ
Phase2
ILIM High-Side MOSFET
Current Limit 		per phase 4.2 5.0 5.8 A
OUTPUT
VREF Internal Reference Voltage 0.6 V
ILKG(FB) Input Leakage Current (FB) EN = High VFB = 0.6 V 1 65 nA
ILKG(RS) Input Leakage Current (RS) VSEL = Low, VRS = 0.6 V 1 65 nA
RRS Internal resistance (RS to GND) VSEL = High, IRS = 1 mA 10 50 Ω
VOUT Output Voltage Range VIN ≥ VOUT 0.6 5.5 V
VOUT Feedback Voltage Accuracy PWM Mode,
VIN ≥ VOUT + 1 V		 TJ = –20°C to 85°C -1% 1%
TJ = –40°C to 125°C -1.4% 1.3%
VOUT Feedback Voltage Accuracy Power Save Mode, L = 0.47 µH,
COUT = 4 x 22 µF(1) 		-1.4% 2.5%
Output Discharge Current(2) EN = Low, VOUT = 2.5 V 120 mA
Load Regulation VOUT = 1.8 V, PWM mode operation 0.02 %/A
Line Regulation 2.6 V ≤ VIN ≤ 5.5 V, VOUT = 1.8 V, IOUT = 6 A, PWM mode operation 0.02 %/V
(1) The output voltage accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output voltage ripple.
(2) For detailed information on output discharge see Active Output Discharge.