JAJSI06A September 2019 – December 2020 TPSM82810 , TPSM82813
PRODUCTION DATA
The device has a power good output with window comparator. The PG pin goes high impedance once the FB pin voltage is above 95% and less than 107% of the nominal voltage, and is driven low once the voltage falls below typically 90% or higher than 110% of the nominal voltage. Table 9-2 shows the typical PG pin logic. The PG pin is an open-drain output and is specified to sink up to 2 mA. The power good output requires a pullup resistor connected to any voltage rail less than VIN. The PG signal can be used for sequencing of multiple rails by connecting to the EN pin of other converters. If not used, the PG pin can be left floating or connected to GND.
DEVICE STATE | PG LOGIC STATUS | ||
---|---|---|---|
HIGH IMPEDANCE | LOW | ||
Enabled (EN = High) | 0.57 V ≤ VFB ≤ 0.642 V |
√ | |
VFB < 0.54 V or VFB > 0.66 V | √ | ||
Shutdown (EN = Low) | √ | ||
UVLO |
2 V ≤ VIN < VUVLO | √ | |
Thermal Shutdown |
TJ > TJSD | √ | |
Power Supply Removal |
VIN < 2 V | √ |
The PG pin has a 40-μs deglitch time on the falling edge.