JAJSOO9A December   2022  – June 2024 TPSM82816

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Precise Enable (EN)
      2. 7.3.2 Output Discharge
      3. 7.3.3 COMP/FSET
      4. 7.3.4 MODE/SYNC
      5. 7.3.5 Spread Spectrum Clocking (SSC)
      6. 7.3.6 Undervoltage Lockout (UVLO)
      7. 7.3.7 Power-Good Output (PG)
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Width Modulation (PWM) Operation
      2. 7.4.2 Power Save Mode Operation (PSM)
      3. 7.4.3 100% Duty-Cycle Operation
      4. 7.4.4 Current Limit and Short-Circuit Protection
      5. 7.4.5 Soft Start / Tracking (SS/TR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Feedforward Capacitor
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Voltage Tracking
      2. 8.3.2 Synchronizing to an External Clock
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
        1. 8.5.2.1 Thermal Consideration
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • VCA|13
  • SIE|14
サーマルパッド・メカニカル・データ
発注情報

7.3.7 Power-Good Output (PG)

The device has a power-good output with window comparator. The PG pin goes high impedance after the FB pin voltage is above 95% and less than 107% of the nominal voltage, and is driven low after the voltage falls below 90% or rises higher than 110% of the nominal voltage (typical). Table 7-2 shows the typical PG pin logic. The PG pin is an open-drain output and is specified to sink up to 2 mA. The power good output requires a pullup resistor connected to any voltage rail less than VIN. The PG signal can be used for sequencing of multiple rails by connecting to the EN pin of other converters. If not used, the PG pin can be left floating or connected to GND.

Table 7-2 Power-Good Pin Logic
DEVICE STATEPG LOGIC STATUS
HIGH IMPEDANCELOW
Enabled (EN = High)0.95 × VFB_NOM ≤ VFB ≤ 1.07 × VFB_NOM√
VFB < 0.9 × VFB_NOM or VFB > 1.1 × VFB_NOM√
Shutdown (EN = Low)√
UVLO2 V ≤ VIN < VUVLO√
Thermal ShutdownTJ > TJSD√
Power Supply RemovalVIN < 2 Vundefined

The PG pin has a 40-μs deglitch time on the falling edge. See Figure 7-1.

TPSM82816 Power-Good Transient and Delay Behavior Figure 7-1 Power-Good Transient and Delay Behavior