JAJSOO9A December   2022  – June 2024 TPSM82816

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Precise Enable (EN)
      2. 7.3.2 Output Discharge
      3. 7.3.3 COMP/FSET
      4. 7.3.4 MODE/SYNC
      5. 7.3.5 Spread Spectrum Clocking (SSC)
      6. 7.3.6 Undervoltage Lockout (UVLO)
      7. 7.3.7 Power-Good Output (PG)
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Width Modulation (PWM) Operation
      2. 7.4.2 Power Save Mode Operation (PSM)
      3. 7.4.3 100% Duty-Cycle Operation
      4. 7.4.4 Current Limit and Short-Circuit Protection
      5. 7.4.5 Soft Start / Tracking (SS/TR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Feedforward Capacitor
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Voltage Tracking
      2. 8.3.2 Synchronizing to an External Clock
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
        1. 8.5.2.1 Thermal Consideration
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • VCA|13
  • SIE|14
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over operating junction remperature range (TJ = –40°C to +125°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = High, no load, device not switching, MODE/SYNC = GND, VOUT = 0.6 V 18 36 μA
ISD Shutdown current EN = GND 0.15 90 μA
VUVLO Undervoltage lockout threshold VIN rising 2.45 2.6 2.7 V
VIN falling 2.1 2.5 2.6 V
TJSD Thermal shutdown threshold TJ rising 180 °C
Thermal shutdown hysteresis TJ falling 15 °C
CONTROL and INTERFACE
VIH,EN Input threshold voltage
EN rising

 1.05 1.1 1.15 V
VIL,EN Input threshold voltage
EN falling

 0.96 1.0 1.05 V
IIH,EN Input leakage current into EN EN = VIN or GND 125 nA
VIH Input-threshold voltage at MODE/SYNC 1.1 V
VIL Input-threshold voltage at MODE/SYNC 0.3 V
IIH Input leakage current into MODE/SYNC 250 nA
fSW PWM switching frequency range MODE/SYNC = high 1.8 2.25 4 MHz
fSW PWM switching frequency COMP/FSET = GND or VIN 2.08 2.25 2.4 MHz
fSW PWM switching frequency tolerance using a resistor from COMP/FSET to GND –12% 12%
fSYNC Frequency range on MODE/SYNC pin for synchronization 1.8 4 MHz
tSync_lock Time to lock to external frequency 50 µs
Duty cycle of synchronization signal at MODE/SYNC 20% 80%
tDelay Enable delay time Time from EN high to device starts switching; VIN applied already 135 270 520 µs
tRamp Output voltage ramp time, SS/TR pin open IOUT = 0 mA, time from device starts switching to power good; device not in current limit 90 150 220 µs
ISS/TR SS/TR source current 8 10 12 µA
RDIS,SS/TR Internal discharge resistance on SS/TR EN = low 0.7 1.1 1.5 kΩ
Tracking gain VFB / VSS/TR 1
Tracking offset VFB when VSS/TR = 0 V ±1 mV
VTH_PG UVP Power-good threshold voltage; dc level VOUT rising (%VFB) 92% 95% 98%
VOUT falling (%VFB) 87% 90% 93%
VTH_PG OVP Power-good threshold voltage; dc level VOUT rising (%VFB) 107% 110% 113%
VOUT falling (%VFB) 104% 107% 111%
VOL,PG Low-level output voltage at PG ISINK_PG = 2 mA 0.01 0.3 V
IIH,PG Input leakage current into PG VPG = 5 V 100 nA
tPG,DLY PG deglitch time for a high level to low level transition on the Power-good output 40 µs
OUTPUT
VFB Feedback voltage 0.6 V
Feedback voltage accuracy PWM mode, VIN ≥ VOUT + 1 V –1% 1%
PFM mode, VIN ≥ VOUT + 1 V, VOUT ≥ 1.5 V, Co,eff ≥ 47 µF –1% 2%
PFM mode, VIN ≥ VOUT + 1 V, VOUT < 1.5 V, Co,eff ≥ 68 µF
 		 –1% 2.5%
Feedback voltage accuracy with voltage tracking VIN ≥ VOUT + 1 V, VSS/TR = 0.3 V, PWM mode –5% 5%
IIH,FB Input leakage current into FB VFB = 0.6 V 1 70 nA
Load regulation PWM mode 0.05 %/A
RDIS Output discharge resistance 30 50 Ω
ton,min Minimum on-time of high-side FET VIN ≥ 3.3 V 45 67 ns
RDP Dropout resistance TPSM82816SIE 100% mode 27 mΩ
RDP Dropout resistance TPSM82814PVCA, TPSM82816PVCA 100% mode 23 mΩ
ILIMH High-side FET switch current limit TPSM82814 DC value, VIN = 3 V to 6 V 5.3 7.2 8.4 A
ILIMH High-side FET switch current limit TPSM82816 DC value, VIN = 3 V to 6 V 7.3 9.2 10.4 A
ILIMNEG Low-side FET negative current limit DC value, MODE/SYNC = high –3 A