JAJSG04A August   2018  – June 2021 TPSM831D31

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  References: DAC
    7. 6.7  Telemetry
    8. 6.8  Current Sense and Calibration
    9. 6.9  Logic Interface Pins: A_EN, A_PGOOD, B_EN, B_PGOOD,RESET
    10. 6.10 Protections: OVP and UVP
    11. 6.11 Typical Characteristics (VIN = 12 V)
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DCAP+ Control
      2. 7.3.2 Setting the Load-Line (DROOP)
      3. 7.3.3 Start-Up Timing
      4. 7.3.4 Load Transitions
      5. 7.3.5 Switching Frequency
      6. 7.3.6 RESET Function
      7. 7.3.7 VID Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Operation With EN Signal Control
      3. 7.4.3 Operation With OPERATION Control
      4. 7.4.4 Operation With EN and OPERATION Control
    5. 7.5 Programming
      1. 7.5.1  PMBus Connections
      2. 7.5.2  PMBus Address Selection
      3. 7.5.3  Supported Commands
      4. 7.5.4  Commonly Used PMBus Commands
      5. 7.5.5  Voltage, Current, Power, and Temperature Readings
        1. 7.5.5.1 (88h) READ_VIN
        2. 7.5.5.2 (89h) READ_IIN
        3. 7.5.5.3 (8Bh) READ_VOUT
        4. 7.5.5.4 (8Ch) READ_IOUT
        5. 7.5.5.5 (8Dh) READ_TEMPERATURE_1
        6. 7.5.5.6 (96h) READ_POUT
        7. 7.5.5.7 (97h) READ_PIN
        8. 7.5.5.8 (D4h) MFR_SPECIFIC_04
      6. 7.5.6  Output Current Sense and Calibration
        1. 7.5.6.1 Reading Individual Phase Currents
          1. 7.5.6.1.1 Reading Total Current
          2. 7.5.6.1.2 51
      7. 7.5.7  Output Voltage Margin Testing
        1. 7.5.7.1 (01h) OPERATION
        2. 7.5.7.2 (26h) VOUT_MARGIN_LOW
        3. 7.5.7.3 (25h) VOUT_MARGIN_HIGH
      8. 7.5.8  Loop Compensation
        1. 7.5.8.1 (D7h) MFR_SPECIFIC_07
        2. 7.5.8.2 (28h) VOUT_DROOP
      9. 7.5.9  Converter Protection and Response
      10. 7.5.10 Output Overvoltage Protection and Response
        1. 7.5.10.1 (40h) VOUT_OV_FAULT_LIMIT
        2. 7.5.10.2 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.5.11 Maximum Allowed Output Voltage Setting
        1. 7.5.11.1 (24h) VOUT_MAX
      12. 7.5.12 Output Undervoltage Protection and Response
        1. 7.5.12.1 (44h) VOUT_UV_FAULT_LIMIT
        2. 7.5.12.2 (45h) VOUT_UV_FAULT_RESPONSE
      13. 7.5.13 Minimum Allowed Output Voltage Setting
        1. 7.5.13.1 (2Bh) VOUT_MIN
      14. 7.5.14 Output Overcurrent Protection and Response
        1. 7.5.14.1 (46h) IOUT_OC_FAULT_LIMIT
        2. 7.5.14.2 (4Ah) IOUT_OC_WARN_LIMIT
        3. 7.5.14.3 (47h) IOUT_OC_FAULT_RESPONSE
        4. 7.5.14.4 Per Phase Overcurrent Limit Thresholds
      15. 7.5.15 Input Under-Voltage Lockout (UVLO)
        1. 7.5.15.1 (35h) VIN_ON
      16. 7.5.16 Input Over-Voltage Protection and Response
        1. 7.5.16.1 (55h) VIN_OV_FAULT_LIMIT
        2. 7.5.16.2 (56h) VIN_OV_FAULT_RESPONSE
      17. 7.5.17 Input Undervoltage Protection and Response
        1. 7.5.17.1 (59h) VIN_UV_FAULT_LIMIT
        2. 7.5.17.2 (5Ah) VIN_UV_FAULT_RESPONSE
      18. 7.5.18 Input Overcurrent Protection and Response
        1. 7.5.18.1 (5Bh) IIN_OC_FAULT_LIMIT
        2. 7.5.18.2 (5Dh) IIN_OC_WARN_LIMIT
        3. 7.5.18.3 (5Ch) IIN_OC_FAULT_RESPONSE
      19. 7.5.19 Overtemperature Protection and Response
        1. 7.5.19.1 (4Fh) OT_FAULT_LIMIT
        2. 7.5.19.2 (51h) OT_WARN_LIMIT
        3. 7.5.19.3 (50h) OT_FAULT_RESPONSE
      20. 7.5.20 Dynamic Phase Shedding (DPS)
        1. 7.5.20.1 (DEh) MFR_SPECIFIC_14
        2. 7.5.20.2 (DFh) MFR_SPECIFIC_15
      21. 7.5.21 NVM Programming
      22. 7.5.22 NVM Security
        1. 7.5.22.1 (FAh) MFR_SPECIFIC_42
      23. 7.5.23 Black Box Recording
        1. 7.5.23.1 (D8h) MFR_SPECIFIC_08
      24. 7.5.24 Board Identification and Inventory Tracking
      25. 7.5.25 Status Reporting
        1. 7.5.25.1 (78h) STATUS_BYTE
        2. 7.5.25.2 (79h) STATUS_WORD
        3. 7.5.25.3 (7Ah) STATUS_VOUT
        4. 7.5.25.4 (7Bh) STATUS_IOUT
        5. 7.5.25.5 (7Ch) STATUS_INPUT
        6. 7.5.25.6 (7Dh) STATUS_TEMPERATURE
        7. 7.5.25.7 (7Eh) STATUS_CML
        8. 7.5.25.8 (80h) STATUS_MFR_SPECIFIC
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitors
        2. 8.2.2.2 Output Capacitors
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Set PMBus Address
        5. 8.2.2.5 PMBus GUI Default Values
      3. 8.2.3 Application Performance Plots
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
  • MOA|28
サーマルパッド・メカニカル・データ
発注情報

(28h) VOUT_DROOP

The VOUT_DROOP command sets the rate, in mV/A (mΩ) at which the output voltage decreases (or increases) with increasing (or decreasing) output current for use with adaptive voltage positioning. This is also referred to as the DC Load Line (DCLL).

VOUT_DROOP is a linear format command. The VOUT_DROOP command must be accessed through Read Word/Write Word transactions.

VOUT_DROOP is a paged register. In order to access VOUT_DROOP for channel A, PAGE must be set to 00h. In order to access the VOUT_DROOP register for channel B, PAGE must be set to 01h. For simultaneous access of channels A and B, the PAGE command must be set to FFh.

VOUT_DROOP
15141312111098
RRRRRRWRWRW
VDROOP_EXPVDROOP_MAN
76543210
RWRWRWRWRWRWRWRW
VDROOP_MAN
LEGEND: R/W = Read/Write; R = Read only
Table 7-26 VOUT_DROOP Register Field Descriptions
BitFieldTypeResetDescription
15:11VDROOP_EXPR11010bLinear two's complement fixed exponent, –6. LSB = 0.015625 mΩ
10:0VDROOP_MANRWNVMLinear two's complement mantissa. See table of acceptable values below, note that Channel A and Channel B support different acceptable values of VOUT_DROOP.

The table below summarizes the acceptable values of VOUT_DROOP for channel A and channel B. Attempts to write any value other than those specified in the table below are treated as invalid data. The device ignores invalid data, sets the appropriate flags in STATUS_CML and STATUS_WORD and asserts the PMB_ALERT to notify the system host of an invalid transaction.

Table 7-27 Acceptable VOUT_DROOP Values
BinVOUT_DROOP (hex)Supported by
Channel A
Supported by
Channel B
DC Load Line (mΩ)
0D000hYesYes0
1D008hYesYes0.125
2D010hYesYes0.25
3D014hYesYes0.3125
4D018hYesYes0.375
5D01ChYesYes0.4375
6D020hYesYes0.5
7D024hYesYes0.5625
8D028hYesYes0.625
9D030hYesYes0.7031
10D033hYesYes0.7969
11D034hYesYes0.8125
12D035hYesYes0.8281
13D036hYesYes0.8438
14D037hYesYes0.8594
15D038hYesYes0.875
16D039hYesNo0.8906
17D03AhYesNo0.9063
18D03BhYesNo0.9219
19D03ChYesNo0.9375
20D03DhYesNo0.9531
21D03EhYesNo0.9688
22D03FhYesNo0.9844
23D040hYesNo1
24D041hYesNo1.0156
25D042hYesNo1.0313
26D043hYesNo1.0469
27D044hYesNo1.0625
28D048hYesNo1.125
29D050hYesNo1.25
30D058hYesNo1.375
31D060hYesNo1.5
32D068hYesNo1.625
33D070hYesNo1.75
34D078hYesNo1.875
35D07ChYesNo1.9375
36D080hYesNo2
37D084hYesNo2.0625
38D088hYesNo2.125
39D08ChYesNo2.1875
40D090hYesNo2.25
41D098hYesNo2.328
42D09BhYesNo2.4218
43D09ChYesNo2.4375
44D09DhYesNo2.4531
45D09EhYesNo2.4687
46D09FhYesNo2.4843
47D0A0hYesNo2.5
48D0A1hYesNo2.5156
49D0A2hYesNo2.5312
50D0A3hYesNo2.5468
51D0A4hYesNo2.5625
52D0A5hYesNo2.5781
53D0A6hYesNo2.5937
54D0A7hYesNo2.609
55D0A8hYesNo2.625
56D0A9hYesNo2.6406
57D0AAhYesNo2.6562
58D0ABhYesNo2.6718
59D0AChYesNo2.6875
60D0B0hYesNo2.75
61D0B8hYesNo2.875
62D0C0hYesNo3
63D0C8hYesNo3.125