JAJSG04A August   2018  – June 2021 TPSM831D31

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  References: DAC
    7. 6.7  Telemetry
    8. 6.8  Current Sense and Calibration
    9. 6.9  Logic Interface Pins: A_EN, A_PGOOD, B_EN, B_PGOOD,RESET
    10. 6.10 Protections: OVP and UVP
    11. 6.11 Typical Characteristics (VIN = 12 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DCAP+ Control
      2. 7.3.2 Setting the Load-Line (DROOP)
      3. 7.3.3 Start-Up Timing
      4. 7.3.4 Load Transitions
      5. 7.3.5 Switching Frequency
      6. 7.3.6 RESET Function
      7. 7.3.7 VID Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Operation With EN Signal Control
      3. 7.4.3 Operation With OPERATION Control
      4. 7.4.4 Operation With EN and OPERATION Control
    5. 7.5 Programming
      1. 7.5.1  PMBus Connections
      2. 7.5.2  PMBus Address Selection
      3. 7.5.3  Supported Commands
      4. 7.5.4  Commonly Used PMBus Commands
      5. 7.5.5  Voltage, Current, Power, and Temperature Readings
        1. 7.5.5.1 (88h) READ_VIN
        2. 7.5.5.2 (89h) READ_IIN
        3. 7.5.5.3 (8Bh) READ_VOUT
        4. 7.5.5.4 (8Ch) READ_IOUT
        5. 7.5.5.5 (8Dh) READ_TEMPERATURE_1
        6. 7.5.5.6 (96h) READ_POUT
        7. 7.5.5.7 (97h) READ_PIN
        8. 7.5.5.8 (D4h) MFR_SPECIFIC_04
      6. 7.5.6  Output Current Sense and Calibration
        1. 7.5.6.1 Reading Individual Phase Currents
          1. 7.5.6.1.1 Reading Total Current
          2. 7.5.6.1.2 51
      7. 7.5.7  Output Voltage Margin Testing
        1. 7.5.7.1 (01h) OPERATION
        2. 7.5.7.2 (26h) VOUT_MARGIN_LOW
        3. 7.5.7.3 (25h) VOUT_MARGIN_HIGH
      8. 7.5.8  Loop Compensation
        1. 7.5.8.1 (D7h) MFR_SPECIFIC_07
        2. 7.5.8.2 (28h) VOUT_DROOP
      9. 7.5.9  Converter Protection and Response
      10. 7.5.10 Output Overvoltage Protection and Response
        1. 7.5.10.1 (40h) VOUT_OV_FAULT_LIMIT
        2. 7.5.10.2 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.5.11 Maximum Allowed Output Voltage Setting
        1. 7.5.11.1 (24h) VOUT_MAX
      12. 7.5.12 Output Undervoltage Protection and Response
        1. 7.5.12.1 (44h) VOUT_UV_FAULT_LIMIT
        2. 7.5.12.2 (45h) VOUT_UV_FAULT_RESPONSE
      13. 7.5.13 Minimum Allowed Output Voltage Setting
        1. 7.5.13.1 (2Bh) VOUT_MIN
      14. 7.5.14 Output Overcurrent Protection and Response
        1. 7.5.14.1 (46h) IOUT_OC_FAULT_LIMIT
        2. 7.5.14.2 (4Ah) IOUT_OC_WARN_LIMIT
        3. 7.5.14.3 (47h) IOUT_OC_FAULT_RESPONSE
        4. 7.5.14.4 Per Phase Overcurrent Limit Thresholds
      15. 7.5.15 Input Under-Voltage Lockout (UVLO)
        1. 7.5.15.1 (35h) VIN_ON
      16. 7.5.16 Input Over-Voltage Protection and Response
        1. 7.5.16.1 (55h) VIN_OV_FAULT_LIMIT
        2. 7.5.16.2 (56h) VIN_OV_FAULT_RESPONSE
      17. 7.5.17 Input Undervoltage Protection and Response
        1. 7.5.17.1 (59h) VIN_UV_FAULT_LIMIT
        2. 7.5.17.2 (5Ah) VIN_UV_FAULT_RESPONSE
      18. 7.5.18 Input Overcurrent Protection and Response
        1. 7.5.18.1 (5Bh) IIN_OC_FAULT_LIMIT
        2. 7.5.18.2 (5Dh) IIN_OC_WARN_LIMIT
        3. 7.5.18.3 (5Ch) IIN_OC_FAULT_RESPONSE
      19. 7.5.19 Overtemperature Protection and Response
        1. 7.5.19.1 (4Fh) OT_FAULT_LIMIT
        2. 7.5.19.2 (51h) OT_WARN_LIMIT
        3. 7.5.19.3 (50h) OT_FAULT_RESPONSE
      20. 7.5.20 Dynamic Phase Shedding (DPS)
        1. 7.5.20.1 (DEh) MFR_SPECIFIC_14
        2. 7.5.20.2 (DFh) MFR_SPECIFIC_15
      21. 7.5.21 NVM Programming
      22. 7.5.22 NVM Security
        1. 7.5.22.1 (FAh) MFR_SPECIFIC_42
      23. 7.5.23 Black Box Recording
        1. 7.5.23.1 (D8h) MFR_SPECIFIC_08
      24. 7.5.24 Board Identification and Inventory Tracking
      25. 7.5.25 Status Reporting
        1. 7.5.25.1 (78h) STATUS_BYTE
        2. 7.5.25.2 (79h) STATUS_WORD
        3. 7.5.25.3 (7Ah) STATUS_VOUT
        4. 7.5.25.4 (7Bh) STATUS_IOUT
        5. 7.5.25.5 (7Ch) STATUS_INPUT
        6. 7.5.25.6 (7Dh) STATUS_TEMPERATURE
        7. 7.5.25.7 (7Eh) STATUS_CML
        8. 7.5.25.8 (80h) STATUS_MFR_SPECIFIC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitors
        2. 8.2.2.2 Output Capacitors
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Set PMBus Address
        5. 8.2.2.5 PMBus GUI Default Values
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

7.5.7 Output Voltage Margin Testing

The TPSM831D31 provides several commands to enable voltage margin testing.

The upper two MARGIN bits in the OPERATION command can be used to toggle the active channel between three states:

  1. Margin None (MARGIN = 0000b). The output voltage target is equal to VOUT_COMMAND.
  2. Margin Low (MARGIN = 01xxb). The output voltage target is equal to VOUT_MARGIN_LOW.
  3. Margin High (MARGIN = 10xxb). The output voltage target is equal to VOUT_MARGIN_HIGH.

In order to use OPERATION, the active channel must be configured for to respect the OPERATION command, via ON_OFF_CONFIG. Output voltage transitions occur at the slew rate defined by VOUT_TRANSITION_RATE.

Table 7-15 Slew Rate Settings
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SLSETSlew rate settingVOUT_TRANSITION_RATE = 0xE050567mV/µs
VOUT_TRANSITION_RATE = 0xE0A0101214mV/µs
VOUT_TRANSITION_RATE = 0xE0F01518mV/µs
VOUT_TRANSITION_RATE = 0xE1402024mV/µs
VOUT_TRANSITION_RATE = 0xE1902530mV/µs
VOUT_TRANSITION_RATE = 0xE1E03036mV/µs
VOUT_TRANSITION_RATE = 0xE2303542mV/µs
VOUT_TRANSITION_RATE = 0xE2804048mV/µs
VOUT_TRANSITION_RATE = 0xE0050.3125mV/µs
VOUT_TRANSITION_RATE = 0xE00A0.625mV/µs
VOUT_TRANSITION_RATE = 0xE00F0.9375mV/µs
VOUT_TRANSITION_RATE = 0xE0141.25mV/µs
VOUT_TRANSITION_RATE = 0xE0191.5625mV/µs
VOUT_TRANSITION_RATE = 0xE01E1.875mV/µs
VOUT_TRANSITION_RATE = 0xE0232.1875mV/µs
VOUT_TRANSITION_RATE = 0xE0282.5mV/µs
VOUT_TRANSITION_RATE = othersInvalid datamV/µs
SLFAVSP and BVSP slew rate SetVID_FastSLSETmV/µs
SLS1AVSP and BVSP slew rate slowSLSET / 4mV/µs
SLSET / 2mV/µs
SLSSAVSP and BVSP slew rate slew rate soft-startMFR_SPEC_13<8> = 0bSLSET / 4mV/µs
MFR_SPEC_13<8> = 1bSLSET / 16mV/µs

The lower two MARGIN bits in the OPERATION command select overvoltage or undervoltage fault handling during margin testing:

  1. Ignore Faults (MARGIN = xx01b) . Overvoltage and undervoltage faults do not trigger during margin tests.
  2. Act on Faults (MARGIN = xx10b). Overvoltage and undervoltage faults trigger during margin tests.

Example: Output Voltage Margin Testing (Ignore Faults)

  1. Write to the PAGE command to select the desired channel (E.g. PAGE = 00h for channel A).
  2. Write VOUT_COMMAND to the desired VID code during Margin None operation.
  3. Write VOUT_MARGIN_LOW to the desired VID code during Margin Low operation.
  4. Write VOUT_MARGIN_HIGH to the desired VID code during Margin High operation.
  5. Write MFR_SPECIFIC_02 to 01h to ensure that the PMBus interface has control of the output voltage.
  6. Set the CMD bit in OPERATION to 1b to ensure the device is configured to respect the OPERATION command.
  7. Margin None. Write OPERATION to 80h.
  8. Margin Low. Write OPERATION to 94h.
  9. Margin High. Write OPERATION to A4h.