JAJSG04A August   2018  – June 2021 TPSM831D31

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  References: DAC
    7. 6.7  Telemetry
    8. 6.8  Current Sense and Calibration
    9. 6.9  Logic Interface Pins: A_EN, A_PGOOD, B_EN, B_PGOOD,RESET
    10. 6.10 Protections: OVP and UVP
    11. 6.11 Typical Characteristics (VIN = 12 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DCAP+ Control
      2. 7.3.2 Setting the Load-Line (DROOP)
      3. 7.3.3 Start-Up Timing
      4. 7.3.4 Load Transitions
      5. 7.3.5 Switching Frequency
      6. 7.3.6 RESET Function
      7. 7.3.7 VID Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Operation With EN Signal Control
      3. 7.4.3 Operation With OPERATION Control
      4. 7.4.4 Operation With EN and OPERATION Control
    5. 7.5 Programming
      1. 7.5.1  PMBus Connections
      2. 7.5.2  PMBus Address Selection
      3. 7.5.3  Supported Commands
      4. 7.5.4  Commonly Used PMBus Commands
      5. 7.5.5  Voltage, Current, Power, and Temperature Readings
        1. 7.5.5.1 (88h) READ_VIN
        2. 7.5.5.2 (89h) READ_IIN
        3. 7.5.5.3 (8Bh) READ_VOUT
        4. 7.5.5.4 (8Ch) READ_IOUT
        5. 7.5.5.5 (8Dh) READ_TEMPERATURE_1
        6. 7.5.5.6 (96h) READ_POUT
        7. 7.5.5.7 (97h) READ_PIN
        8. 7.5.5.8 (D4h) MFR_SPECIFIC_04
      6. 7.5.6  Output Current Sense and Calibration
        1. 7.5.6.1 Reading Individual Phase Currents
          1. 7.5.6.1.1 Reading Total Current
          2. 7.5.6.1.2 51
      7. 7.5.7  Output Voltage Margin Testing
        1. 7.5.7.1 (01h) OPERATION
        2. 7.5.7.2 (26h) VOUT_MARGIN_LOW
        3. 7.5.7.3 (25h) VOUT_MARGIN_HIGH
      8. 7.5.8  Loop Compensation
        1. 7.5.8.1 (D7h) MFR_SPECIFIC_07
        2. 7.5.8.2 (28h) VOUT_DROOP
      9. 7.5.9  Converter Protection and Response
      10. 7.5.10 Output Overvoltage Protection and Response
        1. 7.5.10.1 (40h) VOUT_OV_FAULT_LIMIT
        2. 7.5.10.2 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.5.11 Maximum Allowed Output Voltage Setting
        1. 7.5.11.1 (24h) VOUT_MAX
      12. 7.5.12 Output Undervoltage Protection and Response
        1. 7.5.12.1 (44h) VOUT_UV_FAULT_LIMIT
        2. 7.5.12.2 (45h) VOUT_UV_FAULT_RESPONSE
      13. 7.5.13 Minimum Allowed Output Voltage Setting
        1. 7.5.13.1 (2Bh) VOUT_MIN
      14. 7.5.14 Output Overcurrent Protection and Response
        1. 7.5.14.1 (46h) IOUT_OC_FAULT_LIMIT
        2. 7.5.14.2 (4Ah) IOUT_OC_WARN_LIMIT
        3. 7.5.14.3 (47h) IOUT_OC_FAULT_RESPONSE
        4. 7.5.14.4 Per Phase Overcurrent Limit Thresholds
      15. 7.5.15 Input Under-Voltage Lockout (UVLO)
        1. 7.5.15.1 (35h) VIN_ON
      16. 7.5.16 Input Over-Voltage Protection and Response
        1. 7.5.16.1 (55h) VIN_OV_FAULT_LIMIT
        2. 7.5.16.2 (56h) VIN_OV_FAULT_RESPONSE
      17. 7.5.17 Input Undervoltage Protection and Response
        1. 7.5.17.1 (59h) VIN_UV_FAULT_LIMIT
        2. 7.5.17.2 (5Ah) VIN_UV_FAULT_RESPONSE
      18. 7.5.18 Input Overcurrent Protection and Response
        1. 7.5.18.1 (5Bh) IIN_OC_FAULT_LIMIT
        2. 7.5.18.2 (5Dh) IIN_OC_WARN_LIMIT
        3. 7.5.18.3 (5Ch) IIN_OC_FAULT_RESPONSE
      19. 7.5.19 Overtemperature Protection and Response
        1. 7.5.19.1 (4Fh) OT_FAULT_LIMIT
        2. 7.5.19.2 (51h) OT_WARN_LIMIT
        3. 7.5.19.3 (50h) OT_FAULT_RESPONSE
      20. 7.5.20 Dynamic Phase Shedding (DPS)
        1. 7.5.20.1 (DEh) MFR_SPECIFIC_14
        2. 7.5.20.2 (DFh) MFR_SPECIFIC_15
      21. 7.5.21 NVM Programming
      22. 7.5.22 NVM Security
        1. 7.5.22.1 (FAh) MFR_SPECIFIC_42
      23. 7.5.23 Black Box Recording
        1. 7.5.23.1 (D8h) MFR_SPECIFIC_08
      24. 7.5.24 Board Identification and Inventory Tracking
      25. 7.5.25 Status Reporting
        1. 7.5.25.1 (78h) STATUS_BYTE
        2. 7.5.25.2 (79h) STATUS_WORD
        3. 7.5.25.3 (7Ah) STATUS_VOUT
        4. 7.5.25.4 (7Bh) STATUS_IOUT
        5. 7.5.25.5 (7Ch) STATUS_INPUT
        6. 7.5.25.6 (7Dh) STATUS_TEMPERATURE
        7. 7.5.25.7 (7Eh) STATUS_CML
        8. 7.5.25.8 (80h) STATUS_MFR_SPECIFIC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitors
        2. 8.2.2.2 Output Capacitors
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Set PMBus Address
        5. 8.2.2.5 PMBus GUI Default Values
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • MOA|28
サーマルパッド・メカニカル・データ
発注情報

7.5.20 Dynamic Phase Shedding (DPS)

The dynamic phase shedding (DPS) feature allows the TPSM831D31 to dynamically select the number of operational phases for each channel, based on the total output current. This increases the total converter efficiency by reducing unnecessary switching losses when the output current is low enough to be supported by a fewer number of phases, than are available in hardware. The MFR_SPECIFIC_14 and MFR_SPECIFIC_15 commands may be used to configure dynamic phase shedding behavior and thresholds.

The DPS_EN bit in MFR_SPECIFIC_14 may be used to enable or disable dynamic phase shedding. Un-setting (writing to 0b) this bit forces each channel to use the maximum number of available phases, regardless of the output current. DPS is disabled as the factory default.

The phase add/drop thresholds, at which phases are added or dropped are configured based on the peak efficiency point per phase. For a given switching frequency/duty cycle, the efficiency of an individual power stage has a "peak" point, at which switching losses become less significant and conduction losses begin to dominate. For a multiphase converter, the optimum efficiency is achieved when all of the power stages operate as close as possible to their peak efficiency point. For example, consider a 4-phase design, with power stages that have a peak efficiency point of 12 A per phase. When the total output current is 25 A, if all four phases were active, each phase would be supplying 6.25 A, and hence would be operating far away from their peak efficiency point. With only two phases active, however, each phase supplies 12.5A, meaning that each power stage is operating close to its peak efficiency point, therefore the total converter efficiency is higher overall.

In order to maintain regulation during severe load transient events, phases may be added immediately whenever the total peak current reaches phase addition thresholds. To prevent chattering, phases are dropped when the total average current falls below phase drop thresholds, after a delay of 85 µs typically. Phases are always added/dropped, in numerical order. For example, phase 3 is added after phase 2, and dropped after phase 4.

The DPS_COURSE_TH bits in MFR_SPECIFIC_15 select the peak efficiency point per phase. Refer to the power stage datasheet to determine the peak efficiency point per phase.

Phase adding thresholds are configured based on the peak efficiency point per phase. Each phase transition has a configurable threshold of 6 A to 12 A above the peak efficiency point. For example, the threshold at which the converter transitions from 2 phases to 3 phases is determined by the DPS_2TO3_FINE_ADD bits in MFR_SPECIFIC_15. When 8 A is selected, the total peak current which causes the third phase to be added is 2 × IEFF(PEAK) + 8 A. See the register descriptions below for more detailed information.

Likewise, phase drop thresholds are configured based on the peak efficiency point per phase. Each phase transition has a configurable threshold of 2A below A to 4 A above the peak efficiency point. For example, the threshold at which the converter transitions from 3 phases to 2 phases is determined by the DPS_3TO2_FINE_DROP bits in MFR_SPECIFIC_14. When 0 A is selected, the total average current which causes the third phase to be dropped is 2 × IEFF(PEAK). See the register descriptions below for more detailed information.

Table 7-55 Dynamic Phase Add and Drop
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDPSTHA1 Dynamic phase adding threshold, 1 to 2 Phases (peak current) Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b); VRIPPLE ≈ 18 A (estimation) 21 23 25 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b); VRIPPLE ≈ 18 A (estimation) 23 25 27 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b); VRIPPLE ≈ 18 A (estimation) 25 27 29 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b); VRIPPLE ≈ 18 A (estimation) 27 29 31 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b); VRIPPLE ≈ 18 A (estimation) 23 25 27 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b); VRIPPLE ≈ 18 A (estimation) 25 27 29 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b); VRIPPLE ≈ 18 A (estimation) 27 29 31 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b); VRIPPLE ≈ 18 A (estimation) 29 31 33 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b); VRIPPLE ≈ 18 A (estimation) 25 27 29 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b); VRIPPLE ≈ 18 A (estimation) 27 29 31 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b); VRIPPLE ≈ 18 A (estimation) 29 31 33 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b); VRIPPLE ≈ 18 A (estimation) 31 33 35 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b); VRIPPLE ≈ 18 A (estimation) 27 29 31 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b); VRIPPLE ≈ 18 A (estimation) 29 31 33 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b); VRIPPLE ≈ 18 A (estimation) 31 33 35 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b); VRIPPLE ≈ 18 A (estimation) 33 35 37 A
VDPSTHS1 Dynamic phase shedding threshold, 2 to 1 phase (average current) Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> = 00b) 4 6 8 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> = 01b) 6 8 10 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> = 10b) 8 10 12 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> = 11b) 10 12 14 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> = 00b) 6 8 10 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> = 01b) 8 10 12 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> = 10b) 10 12 14 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> = 11b) 12 14 16 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> = 00b) 8 10 12 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> = 01b) 10 12 14 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> = 10b) 12 14 16 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> = 11b) 14 16 18 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> = 00b) 10 12 14 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> = 01b) 12 14 16 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> = 10b) 14 16 18 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> = 11b) 16 18 20 A
VDPSTHA2 Dynamic phase adding threshold, 2 to 3 phases (peak current) Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b); VRIPPLE = 14 A (estimation) 32.5 35 37.5 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b); VRIPPLE = 14 A (estimation) 34.5 37 39.5 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b); VRIPPLE = 14 A (estimation) 36.5 39 41.5 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> = 11b); VRIPPLE = 14 A (estimation) 38.5 41 43.5 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b); VRIPPLE = 14 A (estimation) 36.5 39 41.5 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b); VRIPPLE = 14 A (estimation) 38.5 41 43.5 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b); VRIPPLE = 14 A (estimation) 40.5 43 45.5 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> = 11b); VRIPPLE = 14 A (estimation) 42.5 45 47.5 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b); VRIPPLE = 14 A (estimation) 40.5 43 45.5 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b); VRIPPLE = 14 A (estimation) 42.5 45 47.5 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b); VRIPPLE = 14 A (estimation) 44.5 47 49.5 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> = 11b); VRIPPLE = 14 A (estimation) 46.5 49 51.5 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b); VRIPPLE = 14 A (estimation) 44.5 47 49.5 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b); VRIPPLE = 14 A (estimation) 46.5 49 51.5 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b); VRIPPLE = 14 A (estimation) 48.5 51 53.5 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> = 11b); VRIPPLE = 14 A (estimation) 50.5 53 55.5 A
VDPSTHS2 Dynamic phase shedding threshold, 3 to 2 phases (average current) Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b) 17.5 20 22.5 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b) 19.5 22 24.5 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b) 21.5 24 26.5 A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> = 00b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b) 23.5 26 28.5 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b) 21.5 24 26.5 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b) 23.5 26 28.5 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b) 25.5 28 30.5 A
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> = 01b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b) 27.5 30 32.5 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b) 25.5 28 30.5 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b) 27.5 30 32.5 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b) 29.5 32 34.5 A
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> = 10b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b) 31.5 34 36.5 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b) 29.5 32 34.5 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b) 31.5 34 36.5 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b) 33.5 36 38.5 A
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> = 11b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b) 35.5 38 40.5 A