JAJSG04 データシート

JAJSG04A August 2018 – June 2021 TPSM831D31

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

MOA|28

サーマルパッド・メカニカル・データ

発注情報

jajsg04a_oa

6.9 Logic Interface Pins: A_EN, A_PGOOD, B_EN, B_PGOOD,RESET

Over recommended operating conditions. Minimum, typical and maximum values are specified through production test or design of the internal controller (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
R_RPGDL	Open-drain pulldown resistance	V_{A_PGOOD} = V_{B_PGOOD} = 0.45 V		36	50	Ω
I_VRTTLK	Open-drain leakage current	SDIO, A_PGOOD, B_PGOOD, Hi Z Leakage, 3.3-V applied in off state	–2	0.2	2	µA
V_AENL	Channel A ENABLE logic low				0.7	V
V_AENH	Channel A ENABLE logic high		0.8			V
V_AENHYS	Channel A ENABLE hysteresis		0.028	0.05	0.07	V
t_AENDIG	Channel A ENABLE deglitch⁽¹⁾		0.2			µs
I_AENH	Channel A I/O 1.1-V leakage	V_{A_EN} = 1.1 V			25	µA
V_BENL	Channel B ENABLE logic low				0.7	V
V_BENH	Channel B ENABLE logic high		0.8			V
V_BENHYS	Channel B ENABLE hysteresis		0.028	0.05	0.07	V
t_BENDIG	Channel B ENABLE deglitch⁽¹⁾		0.2			µs
t_AENVRRDYF	Channel A ENABLE low to A_PGOOD low	From A_EN low to A_PGOOD low			1.5	µs
I_BENH	Channel B I/O 1.1-V leakage	V_BENH = 1.1 V			25	µA
V_RSTL	RESET logic low				0.8	V
V_RSTH	RESET logic high⁽¹⁾		1.09			V
t_RSTTDLY	RESET delay time			1		µs

(1) Specified by design. Not production tested.