JAJSCR3A December 2016 – July 2017 TPSM84A21
PRODUCTION DATA.
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 20 and Figure 22 show typical, top-side PCB layouts. Some considerations for an optimized layout are:
The layout shown in Figure 20 shows the minimum solution size with only a single voltage setting resistor (R1) as the only additional required component. Figure 21 shows a typical internal PCB layer with a trace connecting the VS+ pin to VOUT near the load.
Figure 22 shows a layout with the placement of additional ceramic input capacitors (C1, C3) and ceramic output capacitors (C2, C4) for designs that require additional ripple reduction or improved transient response. Figure 23 shows a typical internal PCB layer with a trace connecting the VS+ pin to VOUT near the load