JAJSMO6A August   2021  – November 2021 TPSM8A28 , TPSM8A29

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using External Bias on VCC Pin
      2. 7.3.2  Enable
      3. 7.3.3  Output Voltage Setting
        1. 7.3.3.1 Remote Sense
      4. 7.3.4  Internal Fixed Soft Start and External Adjustable Soft Start
      5. 7.3.5  External REFIN for Output Voltage Tracking
      6. 7.3.6  Frequency and Operation Mode Selection
      7. 7.3.7  D-CAP3™ Control
      8. 7.3.8  Low-Side FET Zero-Crossing
      9. 7.3.9  Current Sense and Positive Overcurrent Protection
      10. 7.3.10 Low-Side FET Negative Current Limit
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Out-Of-Bounds (OOB) Operation
      14. 7.3.14 Output Voltage Discharge
      15. 7.3.15 UVLO Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-Mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Powering the Device From a 12-V Bus
      4. 7.4.4 Powering the Device From a 5.0-V Bus
      5. 7.4.5 Powering the Device From a Split-Rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setting Point
        2. 8.2.2.2  Choose the Inductor
        3. 8.2.2.3  Set the Current Limit (TRIP)
        4. 8.2.2.4  Choose the Output Capacitor
        5. 8.2.2.5  Choose the Input Capacitors (CIN)
        6. 8.2.2.6  Soft-Start Capacitor (SS/REFIN Pin)
        7. 8.2.2.7  EN Pin Resistor Divider
        8. 8.2.2.8  VCC Bypass Capacitor
        9. 8.2.2.9  BOOT Capacitor
        10. 8.2.2.10 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance on the TI EVM
    3. 10.3 EMI
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.9 Current Sense and Positive Overcurrent Protection

For a buck converter, during the on time of the high-side FET, the switch current increases at a linear rate determined by the following:

  • input voltage
  • output voltage
  • the on time
  • the output inductor value

During the on time of the low-side FET, this current decreases linearly. The average value of the switch current equals to the load current.

The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley current detect control circuit. The inductor current is monitored during the on time of the low-side FET by measuring the low-side FET drain-to-source current. If the measured drain-to-source current of the low-side FET is above the current limit threshold, the low-side FET stays ON until the current level becomes lower than the current limit threshold. This type of behavior reduces the average output current sourced by the device. During an overcurrent condition, the current to the load exceeds the current to the output capacitors. Thus, the output voltage tends to decrease. Eventually, when the output voltage falls below the undervoltage-protection threshold (80%), the UVP comparator detects it and shuts down the device after a wait time of 68 µs. The device then enters a hiccup sleep period for approximately 14 ms. After this waiting period, the device attempts to start up again/remains latched off state (both high-side and low-side FETs are latched off) until a reset of VIN or a re-toggling on the EN pin. Figure 7-3 shows the cycle-by-cycle valley current limit behavior as well as the wait time before the device shuts down.

If an OCL condition happens during start-up, the device still has cycle-by-cycle current limit based on low-side valley current. After soft start is finished, the UV event, which is caused by the OC event, shuts down the device and enters Hiccup mode with a wait time of 68 µs.

The resistor, RTRIP, connected from the TRIP pin to AGND sets current limit threshold. ±1% tolerance resistor is highly recommended because a worse tolerance resistor provides less accurate OCL threshold.

To protect the device from unexpected connection on the TRIP pin, an internal fixed OCL clamp is implemented. This internal OCL clamp limits the maximum valley current on LS FET when TRIP pin has too small resistance to AGND, or is accidently shorted to ground.

Equation 5. GUID-66CEEB06-5257-498D-8B78-E21C6D042F1C-low.gif

where

  • IOCLIM is overcurrent limit threshold for load current in A
  • RTRIP is TRIP resistor value in Ω
  • VIN is input voltage value in V
  • VO is output voltage value in V
  • L is output inductor value in µH
  • fSW is switching frequency in MHz
GUID-0F064652-994C-43E1-B9B2-A347D7169361-low.pngFigure 7-3 Overcurrent Protection