JAJSMM7A August 2022 – September 2023 TPSM8D6B24
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INPUT SUPPLY | |||||||
VAVIN | Input supply voltage range | Controller input voltage with internal LDO | 4.25 | 18 | V | ||
VAVIN | Input supply voltage range | Controller input voltage with valid external bias | 2.95 | 18 | |||
VPVIN | Power stage voltage range | Power stage input voltage with internal LDO | 4.25 | 16 | |||
VPVIN | Power stage voltage range | Power stage input voltage with valid external bias | 2.95 | 16 | |||
IAVIN | Input operating current | Converter not switching, each phase | 12.5 | 17 | mA | ||
AVIN UVLO | |||||||
VAVINuvlo | Analog input voltage UVLO for power on reset (PMBus communication) | Enable threshold | 2.5 | 2.7 | V | ||
Analog input voltage UVLO for disable | 2.09 | 2.3 | V | ||||
Analog input voltage UVLO hysteresis | 250 | mV | |||||
tdelay(uvlo_PMBus) | Delay from AVIN UVLO to PMBus ready to communicate | AVIN = 3 V | 8 | ms | |||
PVIN UVLO | |||||||
VIN_ON | Power input turn-on voltage | Factory default setting | 2.75 | V | |||
Programmable range | 2.75 | 15.75 | |||||
Resolution | 0.25 | ||||||
Accuracy | –5% | 5% | |||||
VIN_OFF | Power input turn-off voltage | Factory default setting | 2.5 | V | |||
Programmable range | 2.5 | 15.5 | |||||
Resolution | 0.25 | ||||||
Accuracy | –5% | 5% | |||||
ENABLE AND UVLO | |||||||
VENuvlo | EN/UVLO voltage rising threshold | 1.05 | 1.1 | V | |||
EN/UVLO voltage falling threshold | 0.9 | ||||||
VENhys | EN/UVLO voltage hysteresis | No external resistors on EN/UVLO | 70 | mV | |||
IENhys | EN/UVLO hysteresis current | VEN/UVLO = 1.1 V | 4.5 | 5.5 | 6.5 | μA | |
EN/UVLO hysteresis current | VEN/UVLO = 0.9 V | –100 | –5 | nA | |||
REMOTE SENSE AMPLIFIER | |||||||
ZRSA | Remote sense input impedance | VOSNS – GOSNS = 1 V | VOSNS to GOSNS | 85 | 130 | 165 | kΏ |
VIRNG(GOSNS) | GOSNS input range for regulation accuracy (1) | VOSNS – GOSNS = 1 V, VOUT_SCALE_LOOP ≤ 0.5 | –0.05 | 0.05 | V | ||
VIRNG(VOSNS) | VOSNS input range for regulation accuracy (1) | GOSNS = AGND, VOUT_SCALE_LOOP ≤ 0.5 | –0.1 | 5.5 | V | ||
REFERENCE VOLTAGE AND ERROR AMPLIFIER | |||||||
VREF | Reference voltage(1) | Default setting | 0.4 | V | |||
Reference voltage range(1) | 0.25 | 0.75 | V | ||||
Reference voltage resolution(1) | 2 –12 | V | |||||
VOUT(ACC) | Output voltage accuracy | VOUT = 1000 mV | –40°C ≤ TJ ≤ 150°C(2) | 0.992 | 1.008 | V | |
VOUT = 500 mV | 0.492 | 0.508 | V | ||||
VOUT = 1500 mV | 1.490 | 1.510 | V | ||||
VOUT = 1000 mV | 0°C ≤ TJ ≤ 125°C(2) | 0.994 | 1.006 | V | |||
VOUT = 500 mV | 0.494 | 0.506 | V | ||||
VOUT = 1500 mV | 1.492 | 1.508 | V | ||||
VOUT = 1000 mV | 0°C ≤ TJ ≤ 85°C(2) | 0.995 | 1.005 | V | |||
VOUT = 500 mV | 0.495 | 0.505 | V | ||||
VOUT = 1500 mV | 1.493 | 1.507 | V | ||||
GmEA | Programmable error amplifier transonductance | 25 | 200 | µS | |||
Resolution(1) | Four settings: 25 μS, 50 μS, 100 μS, 200 μS | 25 | |||||
Unloaded bandwidth(1) | 8 | MHz | |||||
RpEA | Programmable parallel resistor range | 5 | 315 | kΩ | |||
Resolution(1) | 5 | ||||||
CintEA | Programmable integrator capacitor range | 1.25 | 18.75 | pF | |||
Resolution(1) | 1.25 | pF | |||||
CpEA | Programmable parallel capacitor range | 6.25 | 193.75 | pF | |||
Resolution(1) | 6.25 | ||||||
CURRENT GM AMPLIFIER | |||||||
GmBUF | Programmable current error amplifier transonductance | 25 | 200 | µS | |||
Resolution(1) | Four settings: 25 µS, 50 µS, 100 µS, 200 µS | 25 | |||||
Unloaded bandwidth(1) | 17 | MHz | |||||
RpBUF | Programmable parallel resistor range | 5 | 315 | kΩ | |||
Resolution(1) | 5 | ||||||
RintBUF | Programmable integrator resistor range(1) | 800 | 1600 | kΩ | |||
Resolution(1) | 800 | ||||||
CintBUF | Programmable integrator capacitor range | 0.3125 | 4.6875 | pF | |||
Resolution(1) | 0.3125 | ||||||
CpBUF | Programmable parallel capacitor range | 3.125 | 96.875 | pF | |||
Resolution(1) | 3.125 | ||||||
OSCILLATOR | |||||||
fSW | Adjustment range(2) | 275 | 1100 | kHz | |||
Switching frequency(2) | 500 | 550 | 600 | ||||
SYNCHRONIZATION | |||||||
VIH(sync) | High-level input voltage | 1.35 | V | ||||
VIL(sync) | Low-level input voltage | 0.8 | |||||
tpw(sync) | Sync input minimum pulse width | 200 | ns | ||||
ΔfSYNC | SYNC pin frequency range from FREQUENCY_SWITCH frequency(1) | –20% | 20% | ||||
VOH(sync) | Sync output high voltage | 100-μA load | VDD5 –0.85V | VDD5 | V | ||
VOL(sync) | Sync output low voltage | 2.4-mA load | 0.4 | V | |||
tPLL | PLL lock time | fsw = 550 kHz, SYNC clock frequency 495 kHz – 605 kHz(1) | 65 | μs | |||
PhaseErr | Phase interleaving error(5) | fsw < 1.1 MHz | 9 | Degree | |||
fsw ≥1.1 MHz | 23 | ns | |||||
RESET | |||||||
VIH(reset) | High-level input voltage(1) | 1.35 | V | ||||
VIL(reset) | Low-level input voltage | 0.8 | |||||
tpw(reset) | Minimum RESET_B pulse width | 200 | ns | ||||
Rpullup(reset) | Internal pullup resistance | VRESET = 0.8 V | RESET# = 1 | 25 | 34 | 55 | kΩ |
Vpullup(reset) | Internal pullup voltage | IRESET = 10 μA | RESET# = 1 | VDD5 – 0.5 | V | ||
VDD5 REGULATOR | |||||||
VVDD5 | Regulator output voltage | Default, IVDD5 = 10 mA | 4.5 | 4.7 | 4.9 | V | |
Programmable range(1) | 3.9 | 5.3 | V | ||||
Resolution | 200 | mV | |||||
VVDD5(do) | Regulator dropout voltage | VAVIN – VVDD5, VAVIN = 4.5 V, IVDD5 = 25 mA | 130 | 285 | mV | ||
VVDD5ON(IF) | Enable voltage on VDD5 for pin-strapping | 2.62 | 2.85 | V | |||
VVDD5OFF(IF) | Disable voltage on VDD5 for pin-strapping | 2.25 | 2.48 | V | |||
VVDD5ON(SW) | Switching enable voltage upon VDD5 | 4.05 | V | ||||
VVDD5OFF(SW) | Switching disable voltage upon VDD5 | 3.10 | V | ||||
VVDD5UV(hyst) | Regulator UVLO voltage hysteresis | 400 | mV | ||||
VBOOT(drop) | Bootstrap voltage drop | IBOOT = 20 mA, VDD5 = 4.5 V | 225 | mV | |||
BP1V5 REGULATOR | |||||||
VBP1V5 | 1.5-V regulator output voltage | VAVIN ≥ 4.5 V, IBP1V5 = 5 mA | 1.42 | 1.5 | 1.58 | V | |
IBP1V5SC | 1.5-V regulator short-circuit current(1) | 30 | mA | ||||
PWM | |||||||
tON(min) | Minimum controllable pulse width(1) | 20 | ns | ||||
tOFF(min) | PWM Minimum off time(1) | 400 | 500 | ns | |||
SOFT START | |||||||
tON_RISE | Soft-start time | Factory default setting | 3 | ms | |||
Programmable range(1)(3) | 0 | 31.75 | |||||
Resolution | 0.25 | ||||||
Accuracy, TON_RISE = 3 ms | –10% | 15% | |||||
tON_MAX_FLT_LT | Upper limit on the time to power up the output | Factory default setting(4) | 0 | ms | |||
Programmable range(1)(4) | 0 | 127.5 | |||||
Resolution | 0.5 | ||||||
Accuracy(1) | –10% | 15% | |||||
tON_DELAY | Turn-on delay | Factory default setting | 0 | ms | |||
Programmable range(1) | 0 | 127.5 | |||||
Resolution | 0.5 | ||||||
Accuracy(1) | –10% | 15% | |||||
SOFT STOP | |||||||
tOFF_FALL | Soft-stop time | Factory default setting(3) | 0.5 | ms | |||
Programmable range(1)(3) | 0 | 31.75 | |||||
Resolution | 0.25 | ||||||
Accuracy, tOFF_FALL = 1 ms | –10% | 15% | |||||
tOFF_DELAY | Turn-off delay | Factory default setting | 0 | ms | |||
Programmable range(1) | 0 | 127.5 | |||||
Resolution | 0.5 | ||||||
Accuracy(1) | –10% | 15% | |||||
VPVINOVF | Power input overvoltage fault limit | Factory default | 21 | V | |||
6 | 20 | ||||||
1 | |||||||
VPVINUVW | Power input undervoltage warning limit | Factory default | 2.5 | V | |||
Programmable range | 5 | 15.75 | |||||
Resolution | 0.25 | ||||||
POWER STAGE | |||||||
RHS | High-side power device on-resistance | VBOOT – VSW = 4.5 V, TJ = 25°C | 4.5 | mΩ | |||
RLS | Low-side power device on-resistance | VVDD5 = 4.5 V, TJ = 25°C | 0.9 | mΩ | |||
Rswpd | SW internal pulldown resistance | 3 | 30 | 35 | kΩ | ||
Vwkdr(on) | Weak high-side gate drive triggering threshold upon PVIN rising | 14.75 | V | ||||
Vwkdr(off) | Weak high-side gate drive recovering threshold upon PVIN falling | 14.35 | V | ||||
tDEAD(LtoH) | Power stage driver dead-time from low-side off to high-side on | VVDD5 = 4.5 V, TJ = 25°C(1) | 6 | ns | |||
tDEAD(HtoL) | Power stage driver dead-time from high-side off to low-side on | VVDD5 = 4.5 V, TJ = 25°C(1) | 6 | ns | |||
CURRENT SHARING | |||||||
ISHARE(acc) | Output current sharing accuracy of two devices defined as the ratio of the current difference between two devices to the sum of the two | IOUT ≥ 10 A per device(5) | –10% | 10% | |||
Output current sharing accuracy of two devices defined as the current difference between each device and the average of all devices | IOUT < 10 A per device(5) | –1 | 1 | A | |||
VVSHARE | VSHARE fault trip threshold | 0.1 | V | ||||
VSHARE fault release threshold | 0.2 | ||||||
LOW-SIDE CURRENT LIMIT PROTECTION | |||||||
tOFF(OC) | Off time between restart attempts(1) | Factory default setting | 7 × tON_RISE | ms | |||
Range | 1 × tON_RISE | 7 × tON_RISE | |||||
IO_OC_FLT_LMT | Output current overcurrent fault threshold | Factory default setting | 52 | A | |||
Programmable range | 8 | 62 | |||||
Resolution | 2 | ||||||
INEGOC | Negative output current overcurrent protection threshold | –20 | |||||
IOC(acc) | Output current overcurrent fault error | IOUT = 20 A | –2 | 4 | A | ||
IOUT = 25 A(5) | –4 | 8 | |||||
IHSOC | Output current overcurrent fault accuracy | IOUT = 10 A | –1 | 2 | A | ||
IOUT = 20 A(5) | –2 | 4 | |||||
HIGH-SIDE SHORT CIRCUIT PROTECTION | |||||||
IHSOC | Ratio of high-side short-circuit protection fault threshold over low-side overcurrent limit | TJ = 25°C(5) | 105% | 150% | 200% | ||
High-side current sense blanking time | 100 | ns | |||||
POWER GOOD (PGOOD) AND OVERVOLTAGE/UNDERVOLTAGE WARNING | |||||||
RPGD | PGD pulldown resistance | IPGD = 5 mA | 30 | 50 | Ω | ||
IPGD(OH) | Output high open drain leakage current into PGD pin | VPGD = 5 V | 15 | µA | |||
VPGD(OL) | PGD pin output low level voltage at no supply voltage | VAVIN = 0, IPGD = 80 μA | 0.8 | V | |||
VOVW | Overvoltage warning threshold (PGD threshold on VOSNS rising) | Factory default, at VOUT_COMMAND (VOC) = 1 V | 106% | 110% | 114% | VOC | |
Range | 103% | 116% | |||||
Resolution | 1% | ||||||
VUVW | Undervoltage warning threshold (PGD threshold on VOSNS falling) | Factory default, at VOUT_COMMAND (VOC) = 1 V | 86% | 90% | 94% | ||
Range | 84% | 97% | |||||
Resolution | 1% | ||||||
VPGD(rise) | PGD release threshold on VOSNS rising and undervoltage warning de-assertion threshold | Factory default, at VOUT_COMMAND (VOC) = 1 V | 95% | ||||
VPGD(fall) | PGD threshold on VOSNS falling and overvoltage warning de-assertion threshold | Factory default, at VOUT_COMMAND (VOC) = 1 V | 105% | ||||
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE FAULT PROTECTION | |||||||
VOVF | Overvoltage fault threshold | Factory default, at VOUT_COMMAND (VOC) = 1 V | Factory default, at VOUT_COMMAND (VOC) = 1 V | 111% | 115% | 119% | VOC |
Range | Factory default, at VOUT_COMMAND (VOC) = 1 V | Factory default, at VOUT_COMMAND (VOC) = 1 V | 105% | 140% | |||
Resolution | Factory default, at VOUT_COMMAND (VOC) = 1 V | Factory default, at VOUT_COMMAND (VOC) = 1 V | 2.5% | ||||
VUVF | Undervoltage fault threshold | Factory default, at VOUT_COMMAND (VOC) = 1 V | Factory default, at VOUT_COMMAND = 1.00 V | 81% | 85% | 89% | |
Range | Factory default, at VOUT_COMMAND = 1.00 V | Factory default, at VOUT_COMMAND = 1.00 V | 60% | 95% | |||
Resolution | Factory default, at VOUT_COMMAND = 1.00 V | Factory default, at VOUT_COMMAND = 1.00 V | 2.5% | ||||
VUVF(max) | Undervoltage fault threshold maximum setting | 91% | 95% | 99% | VOC | ||
VOVF(fix)OFF | Fixed overvoltage fault threshold | Factory default, at VOUT_COMMAND (VOC) = 1 V | Factory default, at VOUT_COMMAND = 1.00 V | 1.15 | 1.2 | 1.25 | V |
Recovery threshold(1) | Factory default, at VOUT_COMMAND = 1.00 V | Factory default, at VOUT_COMMAND = 1.00 V | 0.4 | ||||
OUTPUT VOLTAGE TRIMMING | |||||||
VOUTRES | Default resolution of VOUT_COMMAND, trim and margin, VOUT_SCALE_LOOP = 0.5 | 1.90 | 1.95 | 2.00 | mV | ||
Programmable range(1) | 2–12 | 2 –5 | V | ||||
VOUT_TRAN_RT | Output voltage transition rate | Factory default setting | 1 | mV/µs | |||
Programmable range(1) | 0.063 | 15.933 | |||||
Accuracy | –10% | 10% | |||||
VOUT_TRAN_RT | Output voltage transition rate | 16-mV/us program rate | 14.4 | 16 | 17.6 | mV/µs | |
VOUT_SCL_LP | Feedback loop scaling factor(1) | Factory default setting | 0.5 | ||||
Programmable range, four discrete settings | 0.125 | 1 | |||||
VOUT_CMD | Output voltage programmable values | Factory default setting | 0.8 | V | |||
Programmable range | VOUT_SCALE_LOOP = 1 (5) | 0.25 | 0.75 | V | |||
VOUT_SCALE_LOOP = 0.5 | 0.25 | 1.5 | |||||
VOUT_SCALE_LOOP = 0.25(5) | 0.25 | 3 | |||||
VOUT_SCALE_LOOP = 0.125(5) | 0.25 | 3.6 | |||||
VOUT_CMD | Output voltage accuracy | Maximum output voltage | VOUT_SCALE_LOOP = 1 | 0.742 | 0.750 | 0.758 | V |
TEMPERATURE SENSE AND THERMAL SHUTDOWN | |||||||
TSD | Bandgap thermal shutdown temperature(1) | 150 | 170 | °C | |||
THYST | Bandgap thermal shutdown hysteresis(1) | 25 | |||||
OT_FLT_LMT | Internal overtemperature fault limit(1) | Factory default setting | 150 | ||||
Programmable range | 0 | 160 | |||||
Resolution | 1 | ||||||
OT_WRN_LMT | Internal overtemperature warning limit(1) | Factory default setting | 125 | ||||
Programmable range | 0 | 160 | |||||
Resolution | 1 | ||||||
TOT(hys) | Internal overtemperature fault, warning hysteresis(1) | Factory default setting | 25 | ||||
MEASUREMENT SYSTEM | |||||||
MVOUT(rng) | Output voltage measurement range(1) | 0 | 6 | V | |||
MVOUT(acc) | Output voltage measurement accuracy | 250 mV < VOUT < 6 V | –2% | 2% | |||
MVOUT(acc) | Output voltage measurement accuracy | 0.5 V < VOUT < 1.25 V | VOUT_SCALE_LOOP = 0.5 | –1% | 1% | ||
MVOUT(lsb) | Output voltage measurement bit resolution(1) | 244 | µV | ||||
MIOUT(rng) | Output current measurement range(1) | –5 | 30 | A | |||
MIOUT(acc) | Output current measurement accuracy(5) | IOUT ≤ 5 A, TJ = 25°C | –1 | 0 | 1 | A | |
MIOUT(acc) | Output current measurement accuracy(5) | IOUT = 10 A, –40°C ≤ TJ ≤ 150°C | –1.5 | 0 | 1.5 | A | |
MIOUT(acc) | Output current measurement accuracy(5) | IOUT = 20 A, –40°C ≤ TJ ≤ 150°C | –2 | 0 | 2 | A | |
MIOUT(acc) | Output current measurement accuracy(5) | IOUT = 10 A, 0°C ≤ TJ ≤ 85°C | –1.3 | 0 | 1.3 | A | |
MIOUT(acc) | Output current measurement accuracy(5) | IOUT = 20 A, 0°C ≤ TJ ≤ 85°C | –1.5 | 0 | 1.5 | A | |
MIOUT(acc) | Output current measurement accuracy | IOUT = 5 A | –1 | 0 | 1 | A | |
IOUT = 10 A | –1.5 | 0 | 1.5 | A | |||
IOUT = 20 A | –2 | 0 | 2 | A | |||
MIOUT(lsb) | Output current measurement bit resolution(1) | 2–6 | A | ||||
MPVIN(rng) | Input voltage measurement range(1) | 0 | 20 | V | |||
MPVIN(acc) | Input voltage measurement accuracy | 4 V < PVIN < 20 V | –3% | 3% | |||
MPVIN(lsb) | Input voltage measurement bit resolution(1) | 2–6 | V | ||||
MTSNS(acc) | Internal temperature sense accuracy(5) | –40°C ≤ TJ ≤ 150°C | –3 | 3 | °C | ||
MTSNS(lsb) | Internal temperature sense bit resolution(1) | 0.25 | |||||
PMBUS INTERFACE + BCX | |||||||
VIH(PMBUS) | High-level input voltage on PMB_CLK, PMB_DATA, BCX_CLK, BCX_DAT | 1.35 | V | ||||
VIL(PMBUS) | Low-level input voltage on PMB_CLK, PMB_DATA, BCX_CLK, BCX_DAT | 0.8 | |||||
IlH(PMBUS) | Input high level current into PMB_CLK, PMB_DATA | –10 | 10 | μA | |||
IIL(PMBUS) | Input low level current into PMB_CLK, PMB_DATA | –10 | 10 | μA | |||
VOL(PMBUS) | Output low level voltage on PMB_DATA, SMB_ALRT, BCX_DAT | VAVIN > 4.5 V, input current to PMB_DATA, SMB_ALRT, BCX_DAT = 20 mA | 0.4 | V | |||
IOH(PMBUS) | Output high level open-drain leakage current into PMB_DATA, SMB_ALRT | Voltage on PMB_DATA, SMB_ALRT = 5.5 V | 10 | μA | |||
IOL(PMBUS) | Output low level open-drain sinking current on PMB_DATA, SMB_ALRT, BCX_DAT | Voltage on PMB_DATA, SMB_ALRT, BCX_DAT = 0.4 V | 20 | mA | |||
fPMBUS_CLK | PMBus operating frequency range | GOSNS = AGND | 10 | 1000 | kHz | ||
CPMBUS | PMBUS_CLK and PMBUS_DATA pin input capacitance(1) | Vpin = 0.1 V to 1.35 V | 5 | pF | |||
NWR_NVM | Number of NVM writable cycles(1) | –40°C to 150°C | 1000 | cycle | |||
tCLK_STCH(max) | Maximum allowable clock stretch(1) | 6 | ms |