JAJSMM7 データシート

JAJSMM7A August 2022 – September 2023 TPSM8D6B24

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

MOW|59

サーマルパッド・メカニカル・データ

発注情報

8.2.2.4 Input Capacitor Selection

The power-stage input-decoupling capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high switching currents demanded when the high-side MOSFET switches on, while providing minimal input-voltage ripple as a result. This effective capacitance includes any DC-bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage with derating. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple to the device during full load. Use Equation 22 to estimate the input RMS current.

Equation 22.

I_{I N (R M S)} = \frac{I_{O U T (M A X)}}{N} \times \sqrt{\frac{V_{O U T}}{V_{I N (M i n)}} \times \frac{(V_{I N (M i n)} - V_{O U T})}{V_{I N (M i n)}}} = \frac{35 A}{1} \times \sqrt{\frac{0.8 V}{5 V} \times \frac{(5 V - 0.8 V)}{5 V}} = 12.8 A

The minimum input capacitance and ESR values for a given input voltage-ripple specification, V_IN(ripple), are shown in Equation 23 and Equation 24. The input ripple is composed of a capacitive portion (V_RIPPLE(cap)) and a resistive portion (V_RIPPLE(esr)).

Equation 23.

C_{I N (M i n)} = \frac{\frac{I_{O U T (M A X)}}{N} \times V_{O U T}}{V_{R I P P L E (c a p)} \times V_{I N (M a x)} \times f_{S W}} = \frac{\frac{35 A}{1} \times 0.8 V}{0.1 V \times 16 V \times 550 k H z} = 31.8 μ F

Equation 24.

E S R_{C I N (M a x)} = \frac{V_{R I P P L E (E S R)}}{\frac{I_{O U T (M a x)}}{N} + \frac{1}{2} I_{R I P P L E}} = \frac{0.2 V}{\frac{35 A}{1} + \frac{1}{2} \times 9.62 A} = 5.02 m Ω

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations because of temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power-regulator capacitors because these components have a high capacitance-to-volume ratio and are fairly stable over temperature. The input capacitor must also be selected with consideration of the DC bias. For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input ripple for V_RIPPLE(cap) and 0.2-V input ripple for V_RIPPLE(esr). Using Equation 23 and Equation 24, the minimum input capacitance for this design is 31.8 µF, and the maximum ESR is 5.02 mΩ. For this design example, four 22-μF, 25-V ceramic capacitors, three 6800-pF, 25-V ceramic capacitors, and two additional 100-μF, 25-V low-ESR electrolytic capacitors in parallel were selected for the power stage with sufficient margin. For all designs a minimum input capacitance of 10 µF is required and a maximum input ripple of 500 mV is recommended.

To minimize the high frequency ringing, the high frequency 6800-pF PVIN bypass capacitors must be placed close to power stage.