JAJSPV2 august 2023 TPSM8S6C24
PRODUCTION DATA
| CMD Address | E4h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary |
| Phased: | No |
| NVM Back-up: | EEPROM or Pin Detect |
| Updates: | On-the-fly |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| SYNC_ DIR | SYNC_EDGE | 10000b | |||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7:6 | SYNC_DIR | RW | NVM | 00b: SYNC disabled 01b: Enable SYNC OUT. 10b: Enable SYNC IN. 11b: Enable Auto Detect SYNC |
| 5 | SYNC_EDGE | RW | NVM | 0b: Synchronize to falling edge of SYNC. 1b: Synchronize to rising edge of SYNC. |
| 4:0 | Not supported | RW | 10000b | Not supported. Set to 10000b. |
Attempts to write (E4h) MFR_SPECIFIC_E4 (SYNC_CONFIG) to any value outside those specified as valid will be considered invalid/unsupported data and cause the TPSM8S6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
When SYNC_DIR = 11b - Enable Auto Detect, the TPSM8S6C24 will select SYNC_IN or SYNC_OUT based on the state of the SYNC pin when the Enable Condition, as defined by ON_OFF_CONFIG is met. If the SYNC_PIN is >2 V or switching faster than 75% of FRQUENCY_SWITCH, SYNC_IN shall be enabled. If the SYNC_PIN is less than 0.8 V and not switching, SYNC_OUT will be selected.
Changing SYNC_DIR from SYNC_IN to SYNC_OUT on a multi-phase stack while conversion is enabled but prevented due to a SYNC_FAULT will result in the internal oscillator operating at 70% of its nominal frequency. Since this is out-side of the compliant SYNC_IN range of the Loop Follower device, this can result in unsynchronized operation.