JAJSPV2 august 2023 TPSM8S6C24
PRODUCTION DATA
| CMD Address | 7Ch |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| Phased: | Yes |
| NVM Back-up: | No |
| Updates: | On-the-fly |
The STATUS_INPUT command returns one data byte with contents as follows. All supported bits can cleared either by CLEAR_FAULTS, or individually by writing 1b to the (7Ch) STATUS_INPUT register in their position, per the PMBus 1.3.1 Part II specification section 10.2.4.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | R | RW | R | RW | R | R | R |
| VIN_OVF | 0 | VIN_UVW | 0 | LOW_VIN | 0 | 0 | 0 |
| LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
7 | VIN_OVF | RW | 0b | 0b: Latched flag indicating PVIN OV fault has NOT occurred. 1b: Latched flag indicating PVIN OV fault has occurred. |
| 6 | VIN_OVW | RW | 0b | Not supported and always set to 0b |
| 5 | VIN_UVW | 0b | 0b: Latched flag indicating PVIN UV warn occurred. 1b: Latched flag indicating PVIN UV warn has occurred. | |
| 4 | Not Supported | R | 0b | Not supported and always set to 0b. |
| 3 | LOW_ VIN | RW | 0b | LIVE (unlatched) status bit. Showing the value of PVIN relative to VIN_ON and
VIN_OFF. 0b: PVIN is ON. 1b: PVIN is OFF. |
| 2:0 | Not Supported | R | 000b | Not supported and always set to 000b. |
All bits which may trigger SMBALERT have a corresponding bit in SMBALERT_MASK .
LOW_VIN vs VIN_UVW
The LOW_VIN bit is an information only (will not assert SMBALERT) flag which indicates that the device is not converting power because its PVIN voltage is less than VIN_ON or the VDD5 voltage is less than its UVLO to enable conversion. LOW_VIN asserts initially at reset but does not assert SMBALERT.
The VIN_UVW bit is a latched status bit, may assert SMBALERT if it is triggered to alert the host of an input voltage issue. VIN_UVW IS masked until the first time the sensed input voltage exceeds the VIN_ON threshold.