JAJSPV2 データシート

JAJSPV2 august 2023 TPSM8S6C24

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

MOY|45
- MPQF759

サーマルパッド・メカニカル・データ

発注情報

jajspv2_oa

8.6.24 (27h) VOUT_TRANSITION_RATE

CMD Address	27h
Write Transaction:	Write Word
Read Transaction:	Read Word
Format:	SLINEAR11 per CAPABILITY
Phased:	No
NVM Back-up:	EEPROM
Updates:	On-the-fly

The VOUT_TRANSITION_RATE sets the slew rate at which any output voltage changes during normal power conversion occur. This commanded rate of change does not apply when the unit is commanded to turn on or to turn off. The units are mV/μs.

Figure 8-30 (27h) VOUT_TRANSITION_RATE Register Map

15	14	13	12	11	10	9	8
RW	RW	RW	RW	RW	RW	RW	RW
VOTR_EXP					VOTR_MAN

7	6	5	4	3	2	1	0
RW	RW	RW	RW	RW	RW	RW	RW
VOTR_MAN

LEGEND: R/W = Read/Write; R = Read only

Table 8-38 Register Field Descriptions

Bit	Field	Access	Reset	Description
15:11	VOTR_ EXP	RW	11100b	Linear format two’s complement exponent. Exponent = -4, LSB = 0.0625 mV/μs
10:0	VOTR_ MAN	RW	NVM	Linear format two’s complement mantissa

Per the TPSM8S6C24 product specification, the following slew rates are supported (see the table below). Note that every binary value between the minimum and maximum values is writeable and readable, but that the actual output voltage slew rate is set to the nearest supported value.

VOUT_TRANSITION RATE can be programmed from 0.067 mV/µs to 15.933 mV/µs.

Attempts to write (27h) VOUT_TRANSITION_RATE to any value outside those specified as valid will be considered invalid/unsupported data and cause the TPSM8S6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.