JAJSPV2 データシート

JAJSPV2 august 2023 TPSM8S6C24

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

MOY|45
- MPQF759

サーマルパッド・メカニカル・データ

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jajspv2_oa

8.6.35 (42h) VOUT_OV_WARN_LIMIT

CMD Address	42h
Write Transaction:	Write Word
Read Transaction:	Read Word
Format:	ULINEAR16 Relative or Absolute per VOUT_MODE

Phased:	No
NVM Back-up:	EEPROM
Updates:	On-the-fly

The VOUT_OV_WARN_LIMIT command sets the value of the output voltage at the sense or output pins that causes an output voltage high warning. This value is typically less than the output overvoltage threshold. The OV_WARN_LIMIT sets an overvoltage threshold relative to the current VOUT_COMMAND. Updates to VOUT_COMMAND do not update the value of VOUT_OV_FAULT_LIMIT when the absolute format is used.

When the sensed output voltage exceeds the VOUT_OV_WARN_LIMIT threshold, the following actions are taken:

Set the VOUT bit in the STATUS_WORD.
Set the VOUT_OVW bit in the STATUS_VOUT register.
Notify the host per PMBus 1.3.1 Part II specification, section 10.2.

Figure 8-41 (42h) VOUT_OV_WARN_LIMIT Register Map

15	14	13	12	11	10	9	8
RW	RW	RW	RW	RW	RW	RW	RW
VOUT_OVW (High Byte)

7	6	5	4	3	2	1	0
RW	RW	RW	RW	RW	RW	RW	RW
VOUT_OVW (Low Byte)

LEGEND: R/W = Read/Write; R = Read only

Table 8-52 Register Field Descriptions

Bit	Field	Access	Reset	Description
15:0	VOUT_ OVW	RW	NVM	Sets the overvoltage warning limit. Format is per VOUT_ MODE.

Hardware Support and Value Mapping

The Hardware for VOUT_OV_WARN_LIMIT is implemented as a fixed percentage of the current output voltage target. Depending on the VOUT_MODE setting, the value written to VOUT_OV_WARN_LIMIT must be mapped to a hardware percentage.

Programmed values not exactly equal to one of the hardware relative values shall be rounded up to the next available relative value supported by hardware. The hardware supports values from 103% to 116% VOUT_COMMAND in 1% steps.

Attempts to write (42h) VOUT_OV_WARN_LIMIT to any value outside those specified as valid, will be considered invalid/unsupported data and cause the TPSM8S6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.