JAJSPV2 august 2023 TPSM8S6C24
PRODUCTION DATA
| CMD Address | ECh |
| Write Transaction: | Write Word |
| Read Transaction: | Read Word |
| Format | Unsigned Word |
| Phased: | No |
| NVM Backup: | EEPROM or Pin Detect |
| Updates: | Conversion Disable: see below. Conversion Enable: Read-Only |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| R | R | R | R | R | R | R | R |
| Reserved 0000h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R | R | RW | RW | RW | RW |
| BCX_START | BCX_STOP | ||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 15:8 | Not supported | R | 0000h | Reserved. Equal 0000h. |
| 7:4 | BCX_START | R | 0000b | BCX_Address for Stack Loop Controller. Equal to 0000b. |
| 3:0 | BCX_STOP | RW | NVM | 0000b: Stand Alone, Single-phase 0001b: One-Loop Follower, 2-phase 0010b: Two Loop Followers, 3-phase 0011b: Three Loop Followers, 4-phase Other: Not supported / Invalid |
Attempts to write (ECh) MFR_SPECIFIC_28 (STACK_CONFIG) to any value outside those specified as valid, will be considered invalid/unsupported data and cause TPSM8S6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.