JAJSMG1 September   2024 TRF1305B1

ADVMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - TRF1305B1
    6. 6.6 Typical Characteristics - TRF1305B1
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Differential RF Amplifier
      2. 7.3.2 Output Common-Mode Control
      3. 7.3.3 Internal Resistor Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
        1. 7.4.1.1 Input Common-Mode Extension
      2. 7.4.2 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Interface Considerations
        1. 8.1.1.1 Single-Ended Input
        2. 8.1.1.2 Differential Input
        3. 8.1.1.3 DC Coupling Considerations
      2. 8.1.2 Gain Adjustment With External Resistors in a Differential Input Configuration
    2. 8.2 Typical Application
      1. 8.2.1 TRF1305x1 as ADC Driver in a Zero-IF Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Supply Voltages
      2. 8.3.2 Single-Supply Operation
      3. 8.3.3 Split-Supply Operation
      4. 8.3.4 Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Typical Characteristics - TRF1305B1

at TA = 25℃, VS+ = 5V, VS– = 0V, floating VOCM, PD, and MODE pins, VICM = midsupply, D2D ac-coupled input/output configuration with ZS = 100Ω, ZL = 100Ω, external input resistor network (see Figure 8-3), inputs de-embedded up to RIN_SER and outputs up to the device pins, ambient temperatures shown, and resistor network included as part of DUT characteristic plots (unless otherwise noted)

TRF1305B1 Power Gain (S21) Across Temperature
PIN = –20dBm at each input pin with 50Ω source
Figure 6-1 Power Gain (S21) Across Temperature
TRF1305B1 Input Return Loss (S11) Across Temperature
PIN = –20dBm at each input pin with 50Ω source
Figure 6-3 Input Return Loss (S11) Across Temperature
TRF1305B1 Output Return Loss (S22) Across Temperature
PIN = –20dBm at each input pin with 50Ω source
Figure 6-5 Output Return Loss (S22) Across Temperature
TRF1305B1 OIP3 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-7 OIP3 Across Temperature
TRF1305B1 OIP3 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-9 OIP3 Across Temperature
TRF1305B1 IMD3 Lower Across Temperature
At (2f1 – f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-11 IMD3 Lower Across Temperature
TRF1305B1 IMD3 Higher Across Temperature
At (2f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-13 IMD3 Higher Across Temperature
TRF1305B1 OIP2 Across Temperature
Per tone PO as shown, 2MHz tone spacing
Figure 6-15 OIP2 Across Temperature
TRF1305B1 IMD2 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-17 IMD2 Across Temperature
TRF1305B1 HD2 Across Output Power and Temperature
 
Figure 6-19 HD2 Across Output Power and Temperature
TRF1305B1 OP1dB Across Supply Voltage and Temperature
 
Figure 6-21 OP1dB Across Supply Voltage and Temperature
TRF1305B1 Noise Figure Across Temperature
 
Figure 6-23 Noise Figure Across Temperature
TRF1305B1 S-Parameters in S2D Configuration
S2D, PIN = –20dBm at each input pin with 50Ω source,
de-embedded up to INP and OUTP/OUTM pins
Figure 6-25 S-Parameters in S2D Configuration
TRF1305B1 OIP3 Across Supply Voltage and Temperature
S2D, PO = –5dBm/tone, 2MHz tone spacing,
de-embedded up to INP and OUTP/OUTM pins
Figure 6-27 OIP3 Across Supply Voltage and Temperature
TRF1305B1 HD2 Across Supply Voltage and Output Power
 
Figure 6-29 HD2 Across Supply Voltage and Output Power
TRF1305B1 OP1dB Across Supply Voltage and Temperature
S2D, de-embedded up to INP and OUTP/OUTM pins
 
Figure 6-31 OP1dB Across Supply Voltage and Temperature
TRF1305B1 Step Response
VS+ = 2.5V, VS– = –2.5V
Figure 6-33 Step Response
TRF1305B1 Power Gain (S21) Across Supply Voltage
PIN = –20dBm at each input pin with 50Ω source
Figure 6-2 Power Gain (S21) Across Supply Voltage
TRF1305B1 Input Return Loss (S11) Across Supply Voltage
PIN = –20dBm at each input pin with 50Ω source
Figure 6-4 Input Return Loss (S11) Across Supply Voltage
TRF1305B1 Reverse Isolation (S12) Across Temperature
PIN = –20dBm at each input pin with 50Ω source
Figure 6-6 Reverse Isolation (S12) Across Temperature
TRF1305B1 OIP3 Across Supply Voltage
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-8 OIP3 Across Supply Voltage
TRF1305B1 OIP3 Across Supply Voltage
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-10 OIP3 Across Supply Voltage
TRF1305B1 IMD3 Lower Across Supply Voltage
At (2f1 – f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-12 IMD3 Lower Across Supply Voltage
TRF1305B1 IMD3 Higher Across Supply Voltage
At (2f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-14 IMD3 Higher Across Supply Voltage
TRF1305B1 OIP2 Across Supply Voltage
Per tone PO as shown, 2MHz tone spacing
Figure 6-16 OIP2 Across Supply Voltage
TRF1305B1 IMD2 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-18 IMD2 Across Temperature
TRF1305B1 HD3 Across Output Power and Temperature
 
Figure 6-20 HD3 Across Output Power and Temperature
TRF1305B1 Differential Input vs Differential Output Power
 
Figure 6-22 Differential Input vs Differential Output Power
TRF1305B1 Noise Figure at Each Single-Ended Output
 
Figure 6-24 Noise Figure at Each Single-Ended Output
TRF1305B1 OIP2 Across Output Power
S2D, de-embedded up to INP and OUTP/OUTM pins
 
Figure 6-26 OIP2 Across Output Power
TRF1305B1 OIP3 Across Supply Voltage and Temperature
S2D, PO = 1dBm/tone, 2MHz tone spacing,
de-embedded up to INP and OUTP/OUTM pins
Figure 6-28 OIP3 Across Supply Voltage and Temperature
TRF1305B1 HD3 Across Supply Voltage and Output Power
 
Figure 6-30 HD3 Across Supply Voltage and Output Power
TRF1305B1 Single-Ended Input vs Differential Output Power
S2D, de-embedded up to INP and OUTP/OUTM pins
 
Figure 6-32 Single-Ended Input vs Differential Output Power
TRF1305B1 Noise Figure in S2D Configuration
S2D, de-embedded up to INP and OUTP/OUTM pins
Figure 6-34 Noise Figure in S2D Configuration