JAJSMG1 September   2024 TRF1305B1

ADVMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - TRF1305B1
    6. 6.6 Typical Characteristics - TRF1305B1
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Differential RF Amplifier
      2. 7.3.2 Output Common-Mode Control
      3. 7.3.3 Internal Resistor Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
        1. 7.4.1.1 Input Common-Mode Extension
      2. 7.4.2 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Interface Considerations
        1. 8.1.1.1 Single-Ended Input
        2. 8.1.1.2 Differential Input
        3. 8.1.1.3 DC Coupling Considerations
      2. 8.1.2 Gain Adjustment With External Resistors in a Differential Input Configuration
    2. 8.2 Typical Application
      1. 8.2.1 TRF1305x1 as ADC Driver in a Zero-IF Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Supply Voltages
      2. 8.3.2 Single-Supply Operation
      3. 8.3.3 Split-Supply Operation
      4. 8.3.4 Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics - TRF1305B1

at TA = 25℃, VS+ = 5V, VS– = 0V, floating VOCM, PD, and MODE pins, VICM = midsupply, D2D ac-coupled input/output with differential source impedance (ZS) = 100Ω, differential output load (ZL) = 100Ω, external input resistor network (see Figure 8-3), and inputs de-embedded up to RIN_SER and outputs up to the device pins (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth (3dB) PIN = –20dBm at each input 7.3 GHz
Small-signal bandwidth (1dB) PIN = –20dBm at each input 6.4
LSBW Large-signal bandwidth (3dB) Differential PIN = –3dBm 7.2 GHz
Large-signal bandwidth (1dB) Differential PIN = –3dBm 6.4
S21 Power gain f = 4GHz 10 dB
Gain variation over temperature f = 4GHz, TA = –40℃ to +85℃ 1
S11 Input return loss f = 10MHz to 7.5GHz –11.3 dB
S12 Reverse isolation f < 10GHz (device enabled) –20 dB
GIMB Differential gain imbalance f < 5GHz, S2D, PIN = –20dBm with 50Ω ZS ±0.2 dB
PHIMB Differential phase imbalance f < 5GHz, S2D, PIN = –20dBm with 50Ω ZS ±2 °
OP1dB Output 1dB compression point f = 500MHz 15.5 dBm
f = 1GHz 16
f = 2GHz 15.7
f = 3GHz 15
f = 4GHz 12.8
f = 5GHz 11
HD2 Second-order harmonic distortion f = 500MHz, VO = 2VPP –84 dBc
f = 1GHz, VO = 2VPP –72
f = 2GHz, VO = 2VPP –62
f = 3GHz, VO = 2VPP –56
f = 4GHz, VO = 2VPP –53
HD3 Third-order harmonic distortion f = 500MHz, VO = 2VPP –68 dBc
f = 1GHz, VO = 2VPP –62
f = 2GHz, VO = 2VPP –61
f = 3GHz, VO = 2VPP –51
f = 4GHz, VO = 2VPP –47
OIP2 Output second-order intercept point f = 500MHz, PO = 1dBm per tone,
2MHz spacing		 85 dBm
f = 1GHz, PO = 1dBm per tone,
2MHz spacing		 71.5
f = 2GHz, PO = 1dBm per tone,
2MHz spacing		 64
f = 3GHz, PO = 1dBm per tone,
2MHz spacing		 58
f = 4GHz, PO = 1dBm per tone,
2MHz spacing		 54.5
f = 5GHz, PO = 1dBm per tone,
2MHz spacing		 56.5
OIP3 Output third-order intercept point f = 500MHz, PO = 1dBm per tone,
2MHz spacing		 43.5 dBm
f = 1GHz, PO = 1dBm per tone,
2MHz spacing		 40
f = 2GHz, PO = 1dBm per tone,
2MHz spacing		 34
f = 3GHz, PO = 1dBm per tone,
2MHz spacing		 32
f = 4GHz, PO = 1dBm per tone,
2MHz spacing		 25.5
f = 5GHz, PO = 1dBm per tone,
2MHz spacing		 19
NF Noise figure f = 500MHz 8 dB
f = 1GHz 8.8
f = 2GHz 10.4
f = 4GHz 13.4
f = 5GHz 13.3
NSD Output noise spectral density f = 500MHz –155.3 dBm/Hz
f = 1GHz –154.8
f = 2GHz –153.8
f = 4GHz –150.7
f = 5GHz –150.7
DC PERFORMANCE
VOD-MAX Max differential output voltage f = 1GHz 4 VPP
Slew rate 2V VO step, S2D configuration,
VS+ = 2.5V, VS– = –2.5V		 25 kV/µs
Output differential offset voltage ±3 mV
Overdrive recovery time From 2 × overdrive of each SE output to each output voltage settling to < ±50mV 6 ns
COMMON-MODE
VICM Input common-mode voltage Default range(1) VS– + 1.5 VS– + 3.5 V
VOCM Output common-mode voltage VS– + 2 VS– + 3 V
Output common-mode offset voltage from VOCM voltage ±10 mV
IMPEDANCE
Zin-SE Single-ended input impedance At INP pin with appropriate termination on INM pin 47 Ω
ZO-DIFF Differential output impedance f = near dc 8 Ω
POWER SUPPLY
IQA Active quiescent current 102 mA
IQPD Power-down quiescent current 25 mA
POWER DOWN
VPD_Hi PD pin logic high Referenced to PAD, see Section 6.1 1.35 V
VPD_Lo PD pin logic low Referenced to PAD, see Section 6.1 0.3 V
IPD_Bias PD bias current (current on PD pin) PD = high (1.8V logic) 15 µA
PD = high (3.3V logic) 30
tON Turn-on time From 50% VPD transition to 90% RF out 25 ns
tOFF Turn-off time From 50% VPD transition to 10% RF out 20 ns
(1) VICM range can be extended closer to VS+ or VS– in D2D configuration. See also Section 7.4.1.