JAJSH31C November   2014  – March 2019 TS3DDR4000

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Static Electrical Characteristics
    6. 6.6 Dynamic Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Non-Volatile Dual In-line Memory Module (NVDIMM) application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Load Isolation Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Dynamic Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
tON Switch turn-on time EN to B VDD = 2.375 V, RL = 50 Ω, VAn = 3.3 V, V/EN = 1.8 V→ 0 V, VSEL1 = VSEL2 = 0 V
(See Figure 12)		 – 65 140 µs
EN to C VDD = 2.375 V, RL = 50 Ω, VAn = 3.3 V, V/EN = 1.8 V→ 0 V, VSEL1 = VSEL2 = 1.8 V
(See Figure 12)		 – 65 140 µs
tSWITCH Switching time between channels for all I/Os SEL to B VDD = 2.375 V, V/EN = 0 V, RL = 50 Ω, VAn = 3.3 V,
(See Figure 13)		 – 65 – ns
SEL to C VDD = 2.375 V, V/EN = 0 V, RL = 50 Ω, VAn = 3.3 V,
(See Figure 13)		 – 50 – ns
tPD Propagation delay Port A to B VDD = 2.375 V,
(See Figure 14)		 – 85 – ps
Port A to C VDD = 2.375 V,
(See Figure 14)		 – 85 – ps
tSKEW(1) Singe-ended skew between channels B0 to B11 VDD = 2.375 V, from any output to any other output – 3 8 ps
C0 to C11 – 3 6 ps
CIN Control input capacitance EN f = 1 MHz, VIN= 0 V – 6 – pF
SEL1 f = 1 MHz, VIN= 0 V – 6 – pF
SEL2 f = 1 MHz, VIN= 0 V – 6 – pF
COFF Switch off capacitance Port A to B f = 1067 MHz, VI/O = 0 V, VSEL1 = VSEL2 = 1.8V – 0.5 – pF
Port A to C f = 1067 MHz, VI/O = 0 V, VSEL1 = VSEL2 = 0 V – 0.5 – pF
CON Switch on capacitance Port A to B f = 1067 MHz, VI/O = 1.2 V, VSEL1 = VSEL2= 0V – 1.0 – pF
Port A to C f = 1067 MHz, VI/O= 1.2 V, VSEL1 = VSEL2 = 1.8V – 1.0 – pF
XTALK Crosstalk between channels B0 to B11 f = 1067 MHz, VSEL1 = VSEL2 = 0 V, RL = 50 Ω – -34 – dB
C0 to C11 f = 1067 MHz, VSEL1 = VSEL2 = 1.8 V, RL = 50 Ω – -31 – dB
OISO Off-isolation Port A to B f = 1067 MHz, VSEL1 = VSEL2 = 1.8 V, RL = 50 Ω – -21 – dB
Port A to C f = 1067 MHz, VSEL1 = VSEL2 = 0 V, RL = 50 Ω – -21 – dB
IL Insertion loss (channel on) Port A to B f = DC, RL = 50 Ω – -0.75 -1 dB
Port A to C f = DC, RL = 50 Ω – -0.75 -1 dB
BWSE -3 dB bandwidth (Single-ended) Port A to B RL = 50 Ω – 5.6 – GHz
Port A to C – 5.6 –
BWDIFF -3 dB bandwidth (Differential) Port A to B RL = 100 Ω – 6 – GHz
Port A to C – 6 –
(1) Verified by design.