SBAS484B September 2010 – December 2016 TSC2014
PRODUCTION DATA.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Voltage range | Analog input X+, Y+, AUX to GND | –0.4 | VDD + 0.1 | V | |
Analog input X–, Y– to GND | –0.4 | VDD + 0.1 | V | ||
VDD/REF pin to GND | –0. | 5 | V | ||
Digital input voltage to GND | –0. | VDD + 0.3 | V | ||
Digital output voltage to GND | –0. | VDD + 0.3 | V | ||
Operating free-air temperature range, TA | –40 | 85 | °C | ||
Storage temperature range, TSTG | –65 | 150 | °C | ||
Junction temperature, TJ Max | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
THERMAL METRIC(1) | TSC2014 | UNIT | |
---|---|---|---|
YZG (DSBGA) | |||
12 PINS | |||
θJA | Junction-to-ambient thermal resistance | 115 | °C/W |
θJCtop | Junction-to-case (top) thermal resistance | 30 | °C/W |
θJB | Junction-to-board thermal resistance | 82 | °C/W |
ψJT | Junction-to-top characterization parameter | 5 | °C/W |
ψJB | Junction-to-board characterization parameter | 75 | °C/W |
θJCbot | Junction-to-case (bottom) thermal resistance | — |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Power Supply, VDD/REF | 1.2 | 3.3 | 3.6 | V | |
TA | Operating free-air temperature | –40 | 85 | °C |
PARAMETER | TEST CONDITIONS | TSC2014 | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | TYP | MAX | |||||
AUXILIARY ANALOG INPUT | |||||||
Input voltage range | 0 | VDD | V | ||||
Input capacitance | 12 | pF | |||||
Input leakage current | –1 | +1 | μA | ||||
Full-scale average input current | VDD = 1.6V, continuous AUX | 2 | μA | ||||
A/D CONVERTER | |||||||
Resolution | Programmable: 10 or 12 bits | 12 | Bits | ||||
No missing codes | 12-bit resolution | 11 | Bits | ||||
Integral linearity | –3 | –0.6 to +0.38 | +3 | LSB(1) | |||
Differential linearity | –2 | –0.46 to +0.49 | +4 | LSB | |||
Offset error | VDD = 1.6V | –5 | 0.53 | +5 | LSB | ||
Gain error | VDD = 1.6V | –3 | 0.32 | +3 | LSB | ||
TOUCH SENSORS | |||||||
PENIRQ 50kΩ pull-up resistor, RIRQ | TA = +25°C, VDD = 1.6V | 50 | kΩ | ||||
X, Y drivers on-resistance | Y+, X+ | TA = +25°C, VDD = 1.6V | 6 | Ω | |||
Y–, X– | TA = +25°C, VDD = 1.6V | 4.5 | Ω | ||||
X, Y drivers drive current(2) | 100ms duration | 50 | mA | ||||
INTERNAL TEMPERATURE SENSOR | |||||||
Temperature range | –40 | +85 | °C | ||||
Resolution | Differential method(3) | VDD = 1.6V | 0.3 | °C/LSB | |||
VDD = 3V | 1.6 | °C/LSB | |||||
TEMP1(4) | VDD = 1.6V | 0.3 | °C/LSB | ||||
VDD = 3V | 1.6 | °C/LSB | |||||
Accuracy | Differential method(3) | VDD = 1.6V | ±3 | °C/LSB | |||
VDD = 3V | ±2 | °C/LSB | |||||
TEMP1(4) | VDD = 1.6V | ±3 | °C/LSB | ||||
VDD = 3V | ±2 | °C/LSB | |||||
INTERNAL OSCILLATOR | |||||||
Clock frequency, fOSC | VDD = 1.2V, TA = +25°C | 3.3 | MHz | ||||
VDD = 1.6V | 3.3 | 3.82 | 4.3 | MHz | |||
VDD = 3.0V, TA = +25°C | 4.1 | MHz | |||||
Frequency drift | VDD = 1.2V | 0.121 | %/°C | ||||
VDD = 1.6V | –0.013 | %/°C | |||||
VDD = 3.0V | –0.028 | %/°C | |||||
DIGITAL INPUT/OUTPUT | |||||||
Logic family | CMOS | ||||||
Logic level | VIH | 1.2V ≤ VDD < 1.6V | 0.7 × VDD | VDD + 0.3 | V | ||
1.6V ≤ VDD ≤ 3.6V | 0.7 × VDD | VDD + 0.3 | V | ||||
VIL | 1.2V ≤ VDD < 1.6V | –0.3 | 0.2 × VDD | V | |||
1.6V ≤ VDD ≤ 3.6V | –0.3 | 0.3 × VDD | V | ||||
IIL | SCL and SDA pins | –1 | 1 | μA | |||
CIN | SCL and SDA pins | 10 | pF | ||||
VOH | IOH = 2 TTL loads | VDD – 0.2 | VDD | V | |||
VOL | IOL = 2 TTL loads | 0 | 0.2 | V | |||
ILEAK | Floating output | –1 | 1 | μA | |||
COUT | Floating output | 10 | pF | ||||
Data format | Straight Binary | ||||||
POWER-SUPPLY REQUIREMENTS | |||||||
Power-supply voltage | |||||||
VDD | Specified performance | 1.2 | 3.6 | V | |||
Quiescent supply current (5) | Filter off, M = W = 1, C[3:0] = (1,0,0,0), RM = 1, CL[1:0] = (0,1), cont AUX mode, fADC = 2MHz, without reading data register | VDD = 1.6V | 420 | 570 | μA | ||
TA = +25°C, filter on, M = 15, W = 7, PSM = 1, C[3:0] = (0,0,0,0), RM = 1, CL[1:0] = (0,1), BTD[2:0] = (1,0,1), 50SSPS, MAVEX = MAVEY = MAVEZ = 1, fADC = 2MHz, High-Speed mode, sensor drivers supply included(6) | VDD = 1.2V | 156 | μA | ||||
VDD = 1.6V | 200 | μA | |||||
VDD = 3.0V | 400 | μA | |||||
TA = +25°C, filter off, M = W = 1, PSM = 1, C[3:0] = (0,0,0,0), RM = 1, CL[1:0] = (0,1), BTD[2:0] = (1,0,1), 50SSPS, MAVEX = MAVEY = MAVEZ = 1, fADC = 2MHz, High-Speed mode, sensor drivers supply included(6) | VDD = 1.2V | 140 | μA | ||||
VDD = 1.6V | 180 | μA | |||||
VDD = 3.0V | 370 | μA | |||||
TA = +25°C, filter off, M = W = 1, C[3:0] = (0,1,0,1), RM = 1, CL[1:0] = (0,1), non-cont AUX mode, fADC = 2MHz, High-Speed mode | VDD = 1.2V, ~27.2kSPS effective rate | 150 | μA | ||||
VDD = 1.6V, ~28.6kSPS effective rate | 200 | μA | |||||
VDD = 3.0V, ~29.1kSPS effective rate | 390 | μA | |||||
TA = +25°C, filter on, M = 7, W = 3, C[3:0] = (0,1,0,1), RM = 1, CL[1:0] = (0,1), MAVEAUX = 1, non-cont AUX mode, fADC = 2MHz, High-Speed mode, full speed | VDD = 1.2V, ~10.3kSPS effective rate | 272 | μA | ||||
VDD = 1.6V, ~11.8kSPS effective rate | 365 | μA | |||||
VDD = 3.0V, ~12.3kSPS effective rate | 683 | μA | |||||
TA = +25°C, filter on, M = 7, W = 3, C[3:0] = (0,1,0,1), RM = 1, CL[1:0] = (0,1), MAVEAUX = 1, non-cont AUX mode, fADC = 2MHz, High-Speed mode, reduced speed (8.2kSPS equivalent rate) | VDD = 1.2V, ~1.17kSPS effective rate | 30.9 | μA | ||||
VDD = 1.6V, ~1.17kSPS effective rate | 36.2 | μA | |||||
VDD = 3.0V, ~1.17kSPS effective rate | 64.9 | μA | |||||
Power-down supply current | TA = +25°C, Not addressed, SCL = SDA = 1, VDD = 1.6V, RESET = 1, PINTDAV = 1 | 0.023 | 0.8 | μA |
TWO-WIRE STANDARD MODE PARAMETERS | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
Reset low time(1) | tWL(RESET) | VDD ≥ 1.6V | 10 | μs | |
1.2V ≤ VDD < 1.6V | 13 | μs | |||
SCL clock frequency | fSCL | 100 | kHz | ||
Bus free time between a STOP and START condition | tBUF | 4.7 | μs | ||
Hold time (repeated) START condition | tHD, STA | 4.0 | μs | ||
Low period of SCL clock | tLOW | 4.7 | μs | ||
High period of the SCL clock | tHIGH | 4.0 | μs | ||
Setup time for a repeated START condition | tSU, STA | 4.7 | μs | ||
Data hold time | tHD, DAT | 0 | 3.45 | μs | |
Data setup time | tSU, DAT | 250 | ns | ||
Rise time of both SDA and SCL signals | tR | Cb = total bus capacitance | 1000 | ns | |
Fall time of both SDA and SCL signals | tF | Cb = total bus capacitance | 300 | ns | |
Setup time for STOP condition | tSU, STO | 4.0 | μs | ||
Capacitive load for each bus line | Cb | Cb = total capacitance of one bus line in pF | 400 | pF | |
Pulse width of spike suppressed | tSP | N/A | N/A | ns |
TWO-WIRE FAST MODE PARAMETERS | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
Reset low time(1) | tWL(RESET) | VDD ≥ 1.6V | 10 | μs | |
1.2V ≤ VDD < 1.6V | 13 | μs | |||
SCL clock frequency | fSCL | 400 | kHz | ||
Bus free time between a STOP and START condition | tBUF | 1.3 | μs | ||
Hold time (repeated) START condition | tHD, STA | 0.6 | μs | ||
Low period of SCL clock | tLOW | 1.3 | μs | ||
High period of the SCL clock | tHIGH | 0.6 | μs | ||
Setup time for a repeated START condition | tSU, STA | 0.6 | μs | ||
Data hold time | tHD, DAT | 0 | 0.9 | μs | |
Data setup time | tSU, DAT | 100 | ns | ||
Rise time of both SDA and SCL signals | tR | Cb = total bus capacitance | 20 + 0.1 × Cb | 300 | ns |
Fall time of both SDA and SCL signals(2) | tF | Cb = total bus capacitance | 20 + 0.1 × Cb | 300 | ns |
Setup time for STOP condition | tSU, STO | 0.6 | μs | ||
Capacitive load for each bus line | Cb | Cb = total capacitance of one bus line in pF | 400 | pF | |
Pulse width of spike suppressed | tSP | 0 | 50 | ns |
TWO-WIRE HIGH-SPEED MODE PARAMETERS | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
Reset low time(1) | tWL(RESET) | VDD ≥ 1.6V | 10 | μs | |
1.2V ≤ VDD < 1.6V | 13 | μs | |||
SCL clock frequency | fSCL | 1.7 | MHz | ||
Hold time (repeated) START condition | tHD, STA | 160 | ns | ||
Low period of SCL clock | tLOW | 320 | ns | ||
High period of the SCL clock | tHIGH | 120 | ns | ||
Setup time for a repeated START condition | tSU, STA | 160 | ns | ||
Data hold time | tHD, DAT | 0 | 150 | ns | |
Data setup time | tSU, DAT | 10 | ns | ||
Rise time of SCL signal | tRCL | Cb = total bus capacitance(2) | 20 | 80 | ns |
Rise time of SDA signal | tRDA | Cb = total bus capacitance(2) | 20 | 160 | ns |
Fall time of SCL signal | tFCL | Cb = total bus capacitance(2) | 20 | 80 | ns |
Fall time of SDA signal | tFDA | Cb = total bus capacitance(2) | 1 | 160 | ns |
Rise time of SCL signal after a repeated START condition and after an acknowledge bit | tRCL1 | Cb = total bus capacitance(2) | 20 | 160 | ns |
Setup time for STOP condition | tSU, STO | 160 | ns | ||
Capacitive load for each bus line | Cb | Cb = total capacitance of one bus line in pF | 400 | pF | |
Pulse width of spike suppressed | tSP | 0 | 10 | ns |
TWO-WIRE HIGH-SPEED MODE PARAMETERS | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
Reset low time(1) | tWL(RESET) | VDD ≥ 1.6V | 10 | μs | |
1.2V ≤ VDD < 1.6V | 13 | μs | |||
SCL clock frequency | fSCL | 3.4 | MHz | ||
Hold time (repeated) START condition | tHD, STA | 160 | ns | ||
Low period of SCL clock | tLOW | 160 | ns | ||
High period of the SCL clock | tHIGH | 60 | ns | ||
Setup time for a repeated START condition | tSU, STA | 160 | ns | ||
Data hold time | tHD, DAT | 0 | 70 | ns | |
Data setup time | tSU, DAT | 10 | ns | ||
Rise time of SCL signal | tRCL | Cb = total bus capacitance(3) | 10 | 40 | ns |
Rise time of SDA signal | tRDA | Cb = total bus capacitance(3) | 10 | 80 | ns |
Fall time of SCL signal | tFCL | Cb = total bus capacitance(3) | 10 | 40 | ns |
Fall time of SDA signal | tFDA | Cb = total bus capacitance(3) | 1 | 80 | ns |
Rise time of SCL signal after a repeated START condition and after an acknowledge bit | tRCL1 | Cb = total bus capacitance(3) | 10 | 80 | ns |
Setup time for STOP condition | tSU, STO | 160 | ns | ||
Capacitive load for each bus line | Cb | Cb = total capacitance of one bus line in pF | 100 | pF | |
Pulse width of spike suppressed | tSP | 0 | 10 | ns |