JAJSC71E May 2016 – May 2019 TUSB1002
PRODUCTION DATA.
PIN | TYPE | INTERNAL PULLUP PULLDOWN | DESCRIPTION | |
---|---|---|---|---|
NAME | RGE | |||
RX1P | 9 | 90Ω Differential Input | Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 1 | |
RX1N | 8 | Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 1 | ||
RX2P | 19 | 90Ω Differential Input | Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 2 | |
RX2N | 20 | Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 2. | ||
TX1P | 22 | 90Ω Differential Output | Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 1. | |
TX1N | 23 | Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 1. | ||
TX2P | 12 | 90Ω Differential Output | Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 2. | |
TX2N | 11 | Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 2. | ||
CH1_EQ1 | 2 | I (4-level) | PU (approx 45K)
PD (approx 95K) |
CH1_EQ1. Configuration pin used to control Rx EQ level for RX1P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of timing. This pin along with CH1_EQ2 allows for up to 16 equalization settings. |
CH1_EQ2 | 3 | I (4-level) | CH1_EQ2. Configuration pin used to control Rx EQ level for RX1P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of timing. This pin along with CH1_EQ1 allows for up to 16 equalization settings. | |
CH2_EQ1 | 16 | I (4-level) | CH2_EQ1. Configuration pin used to control Rx EQ level for RX2P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of timing. This pin along with CH2_EQ2 allows for up to 16 equalization settings. | |
CH2_EQ2 | 17 | I (4-level) | CH2_EQ2. Configuration pin used to control Rx EQ level for RX2P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of timing. This pin along with CH2_EQ1 allows for up to 16 equalization settings. | |
EN | 5 | I (2-level) | PU (approx 400 K) | EN. Places TUSB1002 into shutdown mode when asserted low. Normal operation when pin is asserted high. When in shutdown, TUSB1002’s receiver terminations will be high impedance and tx/rx channels will be disabled. |
CFG1 | 4 | I (4-level) | PU (approx 45K)
PD (approx 95K) |
CFG1. This pin along with CFG2 will select VOD linearity range and DC gain for both channels 1 and 2. The state of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of timing. Refer to Table 3 for VOD linearity range and DC gain options. |
CFG2 | 15 | I (4-level) | CFG2. This pin along with CFG1 will set VOD linearity range and DC gain for both channels 1 and 2. The state of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of timing. Refer to Table 3 for VOD linearity range and DC gain options. | |
MODE | 7 | I (4-level) | PU (approx 45 K)
PD (approx 95K) |
MODE. This pin is for selecting different modes of operation. The state of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of timing.
0 = Test Mode. TI Internal Use Only. R = PCIe / Test Mode. PCIe Mode and TI Internal use only F = USB3.1 Dual Channel Operation enabled (TUSB1002 normal mode). 1 = USB3.1 Single-channel operation. |
RSVD1 | 24 | O | RSVD1. Under normal operation, this pin will be driven low by TUSB1002. Recommend leaving this pin unconnected on PCB. | |
SLP_S0# | 14 | I (2-level) | PU (approx 400 K) | SLP_S0#. This pin when asserted low will disable Receiver Detect functionality. While this pin low and TUSB1002 is in U2/U3, TUSB1002 disables LOS and LFPS detection circuitry and Rx termination for both channels will remain enabled. If this pin is low and TUSB1002 is in Disconnect state, the Rx detect functionality is disabled and Rx termination for both channels will be disabled. If the system SoC does not support a GPIO that indicates system sleep state, then it is recommended to leave this pin unconnected.
0 – Rx Detect disabled 1 – Rx Detect enabled |
NC | No Connect. Leave unconnected on PCB. | |||
VCC | 1, 13 | Power | 3.3 V (±10%) Supply. | |
GND | 6, 10, 18, 21 | GND | Ground | |
Thermal pad | Thermal pad. Recommend connecting to a solid ground plane. |