JAJSDH9D August   2017  – May 2019 TUSB1042I

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      TUSB1042Iのアイ・ダイアグラム
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  DCI Specific Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 4-level Inputs
      3. 8.3.3 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 Linear EQ Configuration
      4. 8.4.4 USB3.1 Modes
      5. 8.4.5 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 9. General Registers
      2. 8.6.2 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 10. USB3.1 Control/Status Registers (0x20)
      3. 8.6.3 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 11. USB3.1 Control/Status Registers (0x21)
      4. 8.6.4 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
        1. Table 12. USB3.1 Control/Status Registers (0x22)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], I2C_EN)
IIH High level input current VCC = 3.6 V; VIN = 3.6 V 20 80 µA
IIL Low level input current VCC = 3.6 V; VIN = 0 V –160 -40 µA
4-Level VTH Threshold 0 / R VCC = 3.3 V 0.55 V
Threshold R/ Float VCC = 3.3 V 1.65 V
Threshold Float / 1 VCC = 3.3 V 2.7 V
RPU Internal pull-up resistance 35 kΩ
RPD Internal pull-down resistance 95 kΩ
2-State CMOS Input (CTL0, TEST1, FLIP) TEST1, CTL0 and FLIP are Failsafe.
VIH High-level input voltage 2 3.6 V
VIL Low-level input voltage 0 0.8 V
RPD Internal pull-down resistance for CTL1 500 kΩ
R(ENPD) Internal pull-down resistance for pin 29 and pin 32 150 kΩ
IIH High-level input current VIN = 3.6 V –25 25 µA
IIL Low-level input current VIN = GND, VCC = 3.6 V –25 25 µA
I2C Control Pins SCL, SDA
VIH High-level input voltage I2C_EN = 0 0.7 x V(I2C) 3.6 V
VIL Low-level input voltage I2C_EN = 0 0 0.3 x V(I2C) V
VOL Low-level output voltage I2C_EN = 0; IOL = 3 mA 0 0.4 V
IOL Low-level output current I2C_EN = 0; VOL = 0.4 V 20 mA
II(I2C) Input current on SDA pin 0.1 x V(I2C) < Input voltage < 3.3 V –10 10 µA
CI(I2C) Input capacitance 10 pF
C(I2C_FM+_BUS) I2C bus capacitance for FM+ (1MHz) 150 pF
C(I2C_FM_BUS) I2C bus capacitance for FM (400kHz) 150 pF
R(EXT_I2C_FM+) External resistors on both SDA and SCL when operating at FM+ (1MHz) C(I2C_FM+_BUS) = 150 pF 620 820 910 Ω
R(EXT_I2C_FM) External resistors on both SDA and SCL when operating at FM (400kHz) C(I2C_FM_BUS) = 150 pF 620 1500 2200 Ω