JAJSDH9D August 2017 – May 2019 TUSB1042I
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Reserved | EQ_OVERRIDE | Reserved | FLIPSEL | CTLSEL[1:0]. | ||
R | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | Reserved | R | 00 | Reserved. |
5 | Reserved | R | 0 | Reserved. |
4 | EQ_OVERRIDE | R/W | 0 | Setting of this field will allow software to use EQ settings from registers instead of value sample from pins.
0 – EQ settings based on sampled state of the EQ pins (SSEQ[1:0], EQ[1:0], and DPEQ[1:0]). 1 – EQ settings based on programmed value of each of the EQ registers |
3 | Reserved | R | 0 | Reserved. |
2 | FLIPSEL | R/W | 0 | FLIPSEL. Refer to Table 4 for this field functionality. |
1:0 | CTLSEL[1:0]. | R/W | 01 | 00 – Disabled. All RX and TX for USB3 are disabled.
01 – USB3.1 enabled. (Default) 10 – Reserved. 11 – Reserved. |