JAJSCE2E August   2016  – January 2023 TUSB1046-DCI

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.1
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 USB3.1 Modes
      6. 7.4.6 Operation Timing – Power Up
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 General Register (address = 0x0A) [reset = 00000001]
      2. 7.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
      3. 7.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
      4. 7.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
      5. 7.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
      6. 7.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
      7. 7.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
      8. 7.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 AC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
USB Gen 2 Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
V(RX-DIFF-PP)Input differential peak-peak voltage swing linear dynamic rangeAC-coupled differential peak-to-peak signal measured post CTLE through a reference channel2000mVpp
V(RX-DC-CM)Common-mode voltage bias in the receiver (DC)02V
R(RX-DIFF-DC)Differential input impedance (DC)Present after a GEN2 device is detected on TXP/TXN72120Ω
R(RX-CM-DC)Receiver DC common mode impedancePresent after a GEN2 device is detected on TXP/TXN1830Ω
Z(RX-HIGH-IMP-DC-POS)Common-mode input impedance with termination disabled (DC)Present when no GEN2 device is detected on TXP/TXN. Measured over the range of 0-500mV with respect to GND.25kΩ
V(SIGNAL-DET-DIFF-PP)Input differential peak-to-peak signal detect assert levelAt 10 Gbps, no input loss, PRBS7 pattern80mV
V(RX-IDLE-DET-DIFF-PP)Input differential peak-to-peak signal detect de-assert LevelAt 10 Gbps, no input loss, PRBS7 pattern60mV
V(RX-LFPS-DET-DIFF-PP)Low frequency periodic signaling (LFPS) detect thresholdBelow the minimum is squelched100300mV
V(RX-CM-AC-P)Peak RX AC common-mode voltageMeasured at package pin150mV
C(RX)RX input capacitance to GNDAt 5 GHz0.51pF
RL(RX-DIFF)Differential return Loss50 MHz – 1.25 GHz at 90 Ω–19dB
5 GHz at 90 Ω–10dB
RL(RX-CM)Common-mode return loss50 MHz – 5 GHz at 90 Ω–10dB
EQ(SS_TX)Receiver equalization for upstream facing portSSEQ[1:0] at 5 GHz11dB
EQ(SS_RX)Receiver equalization for downstream facing portsEQ[1:0] at 5 GHz9dB
USB Gen 2 Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
VTX(DIFF-PP)Transmitter dynamic differential voltage swing range.1600mVPP
VTX(RCV-DETECT)Amount of voltage change allowed during receiver detection600mV
VTX(CM-IDLE-DELTA)Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS–600600mV
VTX(DC-CM)Common-mode voltage bias in the transmitter (DC)02V
VTX(CM-AC-PP-ACTIVE)Tx AC common-mode voltage activeMax mismatch from Txp + Txn for both time and amplitude100mVPP
VTX(IDLE-DIFF-AC-PP)AC electrical idle differential peak-to-peak output voltageAt package pins010mV
VTX(IDLE-DIFF-DC)DC electrical idle differential output voltageAt package pins after low pass filter to remove AC component014mV
VTX(CM-DC-ACTIVE-IDLE-DELTA)Absolute DC common-mode voltage between U1 and U0At package pin200mV
RTX(DIFF)Differential impedance of the driver75120Ω
CAC(COUPLING)AC coupling capacitor75265nF
RTX(CM)Common-mode impedance of the driverMeasured with respect to AC ground over
0–500 mV		1830Ω
ITX(SHORT)TX short circuit currentTX± shorted to GND67mA
CTX(PARASITIC)TX input capacitance for return lossAt package pins, at 5 GHz1.25pF
RLTX(DIFF)Differential return loss50 MHz – 1.25 GHz at 90 Ω-15dB
5 GHz at 90 Ω-13dB
RLTX(CM)Common-mode return loss50 MHz – 5 GHz at 90 Ω-13dB
AC Characteristics
CrosstalkDifferential crosstalk between TX and RX signal pairsat 5 GHz–30dB
C(P1dB-LF)Low frequency 1-dB compression pointat 100 MHz, 200 mVPP < VID
< 2000 mVPP		1300mVPP
C(P1dB-HF)High frequency 1-dB compression pointat 5 GHz, 200 mVPP < VID
< 2000 mVPP		1000mVPP
fLFLow frequency cutoff200 mVPP< VID < 2000 mVPP2050kHz
TX output deterministic jitter200 mVPP < VID < 2000 mVPP, PRBS7, 10 Gbps0.11UIpp
200 mVPP < VID < 2000 mVPP, PRBS7, 8.1 Gbps0.08UIpp
TX output total jitter200 mVPP < VID < 2000 mVPP, PRBS7, 10 Gbps0.15UIpp
200 mVPP < VID < 2000 mVPP, PRBS7, 8.1 Gbps0.135UIpp
DisplayPort Receiver (DP[3:0]p or DP[3:0]n)
VID(PP)Peak-to-peak input differential dynamic voltage range2000V
VICInput common mode voltage02V
C(AC)AC coupling capacitance75265nF
EQ(DP)Receiver equalizationDPEQ[1:0] at 4.05 GHz14dB
dRData rateHBR38.1Gbps
R(ti)Input termination resistance80100120Ω
DisplayPort Transmitter (TX1p or TX1n, TX2p or TX2n, RX1p or RX1n, RX2p or RX2n)
ITX(SHORT)TX short circuit currentTX± shorted to GND67mA
VTX(DC-CM)Common-mode voltage bias in the transmitter (DC)00V
AUXp or AUXn and SBU1 or SBU2
RONOutput ON resistanceVCC = 3.3V; VI = 0 to 0.4 V for AUXp;
VI = 2.7 V to 3.6 V for AUXn		510Ω
ΔRONON resistance mismatch within pairVCC = 3.3 V; VI = 0 to 0.4 V for AUXP;
VI = 2.7 V to 3.6 V for AUXN		2.5Ω
RON(FLAT)ON resistance flatness (RON max – RON min) measured at identical VCC and temperatureVCC = 3.3 V; VI = 0 to 0.4 V for AUXp;
VI = 2.7 V to 3.6 V for AUXn		2Ω
V(AUXP_DC_CM)AUX Channel DC common mode voltage for AUXp and SBU1.VCC = 3.3 V00.4V
V(AUXN_DC_CM)AUX Channel DC common mode voltage for AUXn and SBU2VCC = 3.3 V2.73.6V
C(AUX_ON)ON-state capacitanceVCC = 3.3 V; CTL1 = 1; VI = 0 V
or 3.3 V		47pF
C(AUX_OFF)OFF-state capacitanceVCC = 3.3 V; CTL1 = 0; VI = 0 V
or 3.3 V		36pF