JAJSKH5A April   2022  – May 2024 TUSB1142

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4.   概要
  5. 3 Pin Configuration and Functions
  6. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Power Supply Characteristics
    6. 4.6  Control I/O DC Electrical Characteristics
    7. 4.7  USB Electrical Characteristics
    8. 4.8  Timing Requirements
    9. 4.9  Switching Characteristics
    10. 4.10 Typical Characteristics
  7. 5 Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Inputs
      2. 6.3.2 USB Receiver Linear Equalization
        1. 6.3.2.1 Linear EQ Configuration
        2. 6.3.2.2 Full Adaptive Equalization
        3. 6.3.2.3 Fast Adaptive Equalization
      3. 6.3.3 USB Transmitter
        1. 6.3.3.1 Linearity VOD
        2. 6.3.3.2 Limited VOD
        3. 6.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 6.3.4 USB 3.2 2:1 MUX Description
      5. 6.3.5 USB Polarity Inversion
      6. 6.3.6 Receiver Detect Control
    4. 6.4 Device Functional Modes
      1. 6.4.1 MODE Pin
      2. 6.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 6.4.3 USB 3.2 Power States
      4. 6.4.4 Disabling U1 and U2
    5. 6.5 Programming
      1. 6.5.1 Pseudocode Examples
        1. 6.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 6.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 6.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 6.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 6.5.1.5 Full AEQ with Linear Redriver Mode
        6. 6.5.1.6 Full AEQ with Limited Redriver Mode
      2. 6.5.2 TUSB1142 I2C Address Options
      3. 6.5.3 TUSB1142 I2C Target Behavior
    6. 6.6 Register Map
      1. 6.6.1 TUSB1142 Registers
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 USB SSTX Receiver Configuration
        2. 7.2.2.2 USB CRX1/2 Receiver Configuration
          1. 7.2.2.2.1 Fixed Equalization
          2. 7.2.2.2.2 Full Adaptive Equalization
          3. 7.2.2.2.3 Fast Adaptive Equalization
        3. 7.2.2.3 ESD Protection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5.3 TUSB1142 I2C Target Behavior

TUSB1142 I2C Write with Data Figure 6-2 I2C Write with Data

The following procedure should be followed to write data to TUSB1142 I2C registers (refer to Figure 6-2):

  1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1142 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB1142 acknowledges the address cycle.
  3. The controller presents the register offset within TUSB1142 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB1142 acknowledges the sub-address cycle.
  5. The controller presents the first byte of data to be written to the I2C register.
  6. The TUSB1142 acknowledges the byte transfer.
  7. The controller may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB1142.
  8. The controller terminates the write operation by generating a stop condition (P).

TUSB1142 I2C Read Without Repeated Start Figure 6-3 I2C Read Without Repeated Start

The following procedure should be followed to read the TUSB1142 I2C registers without a repeated Start (refer Figure 6-3).

  1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1142 7-bit address and a zero-value “W/R” bit to indicate a read cycle.
  2. The TUSB1142 acknowledges the 7-bit address cycle.
  3. Following the acknowledge the controller continues sending clock.
  4. The TUSB1142 transmit the contents of the memory registers MSB-first starting at register 00h or last read register offset+1. If a write to the I2C register occurred prior to the read, then the TUSB1142 shall start at the register offset specified in the write.
  5. The TUSB1142 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  6. If an ACK is received, the TUSB1142 transmits the next byte of data as long as controller provides the clock. If a NAK is received, the TUSB1142 stops providing data and waits for a stop condition (P).
  7. The controller terminates the write operation by generating a stop condition (P).

TUSB1142 I2C Read with Repeated Start Figure 6-4 I2C Read with Repeated Start

The following procedure should be followed to read the TUSB1142 I2C registers with a repeated Start (refer Figure 6-4).

  1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1142 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB1142 acknowledges the 7-bit address cycle.
  3. The controller presents the register offset within TUSB1142 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB1142 acknowledges the register offset cycle.
  5. The controller presents a repeated start condition (Sr).
  6. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1142 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  7. The TUSB1142 acknowledges the 7-bit address cycle.
  8. The TUSB1142 transmit the contents of the memory registers MSB-first starting at the register offset.
  9. The TUSB1142 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  10. If an ACK is received, the TUSB1142 transmits the next byte of data as long as controller provides the clock. If a NAK is received, the TUSB1142 stops providing data and waits for a stop condition (P).
  11. The controller terminates the read operation by generating a stop condition (P).

TUSB1142 I2C Write Without Data Figure 6-5 I2C Write Without Data

The following procedure should be followed for setting a starting sub-address for I2C reads (refer to Figure 6-5).

  1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1142 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB1142 acknowledges the address cycle.
  3. The controller presents the register offset within TUSB1142 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB1142 acknowledges the register offset cycle.
  5. The controller terminates the write operation by generating a stop condition (P).

Note:

After initial power-up, if no register offset is included for the read procedure (refer to Figure 6-3), then reads start at register offset 00h and continue byte by byte through the registers until the I2C controller terminates the read operation. During a read operation, the TUSB1142 auto-increments the I2C internal register address of the last byte transferred independent of whether or not an ACK was received from the I2C controller.