JAJSKH5A April   2022  – May 2024 TUSB1142

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4.   概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Power Supply Characteristics
    6. 4.6  Control I/O DC Electrical Characteristics
    7. 4.7  USB Electrical Characteristics
    8. 4.8  Timing Requirements
    9. 4.9  Switching Characteristics
    10. 4.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Inputs
      2. 6.3.2 USB Receiver Linear Equalization
        1. 6.3.2.1 Linear EQ Configuration
        2. 6.3.2.2 Full Adaptive Equalization
        3. 6.3.2.3 Fast Adaptive Equalization
      3. 6.3.3 USB Transmitter
        1. 6.3.3.1 Linearity VOD
        2. 6.3.3.2 Limited VOD
        3. 6.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 6.3.4 USB 3.2 2:1 MUX Description
      5. 6.3.5 USB Polarity Inversion
      6. 6.3.6 Receiver Detect Control
    4. 6.4 Device Functional Modes
      1. 6.4.1 MODE Pin
      2. 6.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 6.4.3 USB 3.2 Power States
      4. 6.4.4 Disabling U1 and U2
    5. 6.5 Programming
      1. 6.5.1 Pseudocode Examples
        1. 6.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 6.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 6.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 6.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 6.5.1.5 Full AEQ with Linear Redriver Mode
        6. 6.5.1.6 Full AEQ with Limited Redriver Mode
      2. 6.5.2 TUSB1142 I2C Address Options
      3. 6.5.3 TUSB1142 I2C Target Behavior
    6. 6.6 Register Map
      1. 6.6.1 TUSB1142 Registers
  9. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 USB SSTX Receiver Configuration
        2. 7.2.2.2 USB CRX1/2 Receiver Configuration
          1. 7.2.2.2.1 Fixed Equalization
          2. 7.2.2.2.2 Full Adaptive Equalization
          3. 7.2.2.2.3 Fast Adaptive Equalization
        3. 7.2.2.3 ESD Protection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  11. Revision History
  12. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Full Adaptive Equalization

The Full AEQ mode attempts to find what it believes is the best equalization value for CRX1 and CRX2 receivers by starting at the lowest EQ value and sweeping through all EQ combinations up to the value programmed into FULLAEQ_UPPER_EQ field. The default is to sweep through nine EQ values (zero to eight). The number of EQ combinations can be adjusted by programming FULLAEQ_UPPER_EQ register. The TUSB1142 also provides the ability to add or subtract some over/under equalization to compensate for channel in front of TUSB1142 by programming OVER_EQ_CTRL field to a non-zero value. If OVER_EQ_SIGN = 0, the TUSB1142 will add the value programmed into OVER_EQ_CTRL to the EQ value determined by the full adaptation. If OVER_EQ_SIGN = 1, the TUSB1142 will subtract the value programmed into OVER_EQ_CTRL from the EQ value determined by the full adaptation. For example, if full adaptation determines the best equalization value to be 4 and OVER_EQ_CTRL is 2 and OVER_EQ_SIGN = 0, the EQ setting used by TUSB1142 will be 6. The TUSB1142 hardware will always limit the sum of OVER_EQ_CTRL and the determined optimal EQ from full adaptation to be less than or equal to 15.

Note: Full AEQ is supported in both pin-strap and I2C mode. In pin-strap mode, enable or disable of Full AEQ is determined by the state of AEQENZ pin.