It is the same as the func_ctrl register with read/set-only property (write '1' to set a particular bit, a write '0' has no-action).

It is the same as the func_ctrl register with read/clear-only property (write '1' to clear a particular bit, a write '0' has no-action).

It is the same as the ifc_ctrl register with read/set-only property (write '1' to set a particular bit, a write '0' has no-action).

It is the same as the ifc_ctrl register with read/clear-only property (write '1' to clear a particular bit, a write '0' has no-action).

It is the same as the otg_ctrl register with read/set-only property (write '1' to set a particular bit, a write '0' has no-action).

It is the same as the otg_ctrl register with read/Clear-only property (write '1' to clear a particular bit, a write '0' has no-action).

It is the same as the usb_int_en_rise register with read/set-only property (write '1' to set a particular bit, a write '0' has no-action).

It is the same as the usb_int_en_rise register with read/clear-only property (write '1' to clear a particular bit, a write '0' has no-action).

It is the same as the usb_int_en_fall register with read/set-only property (write '1' to set a particular bit, a write '0' has no-action)

It is the same as the usb_int_en_fall register with read/clear-only property (write '1' to clear a particular bit, a write '0' has no-action).

The PHY follows the rules defined in Table 26 of the ULPI spec for setting any latch register bit. It is important to note that if register read data is returned to the Link in the same cycle that a USB Interrupt Latch bit is to be set, the interrupt condition is given immediately in the register read data and the Latch bit is not set.

Note that it is optional for the Link to read the USB Interrupt Latch register in Synchronous Mode because the RX CMD byte already indicates the interrupt source directly

It is the same as the scratch_reg register with read/set-only property (write '1' to set a particular bit, a write '0' has no-action).

It is the same as the scratch_reg with read/clear-only property (write '1' to clear a particular bit, a write '0' has no-action).

When SW_CONTROL= 0, HWDETECT bit is read-only. This bit indicates if the transceiver is connected to a Charging Port (Dedicated Charging Port or Charging Downstream Port ).

0b: No charger detected.

1b: Charger detected.

Note when SW_CONTROL=0, hardware controls the CHRG_DET pin with the same logic described below for SW_CONTROL=1 case. When SW_CONTROL=1, HWDETECT is writeable. This bit allows manual control over the logic levels on the CHRG_DET pin.

0b: CHRG_DET is externally pulled LOW (CHRG_DET_POL is HIGH) or CHRG_DET is externally pulled HIGH (CHRG_DET_POL is LOW).

1b: CHRG_DET is driven LOW (CHRG_DET_POL is LOW) or CHRG_DET is driven HIGH (CHRG_DET_POL is HIGH)

This bit controls whether DP is allowed to send V_{DAT_SRC}, which is a sensing voltage for charger detection. This bit also enables I_{DAT_SINK} on DM and V_{DAT_REF}. (Used when manual control over the charger detection is needed.) Note when SW_CONTROL=0, this bit is read-only. In this case hardware controls I_{DAT_SINK} and V_{DAT_REF} with the same logic described below for SW_CONTROL=1 case.

When SW_CONTROL=1, DP_VSRC_EN is writeable:

0b: No transmission of sensing voltage is performed. IDAT_SINK and VDAT_REF are disabled.

1b: DP transmits sensing voltage; enables IDAT_SINK and VDAT_REF.

This bit indicates the presence of a voltage level higher that VDAT_REF on the DM. (Used when manual control over the charger detection is needed.)

0b: Voltage on DM is lower than VDAT_REF

1b: Voltage on DM is higher than VDAT_REF

Enables the weak pull-up resistor on the DP pin in synchronous mode when VBUS is above the VSESS_VLD threshold.

0b: DP weak pull-up is disabled.

1b: DP weak pull-up is enabled when VBUS > VSESS_VLD

Detection of DP/DM condition while this bit is set should be done through LINESTATE<1:0>bits in DEBUG register (0x15) or through RX CMD.

This bit indicates if a Charging Port has been detected.

0b: A Charging Port has not been detected, or charger detection has not been activated. (Identical to HWDETECT)

1b: A Charging Port has been detected (Identical to HWDETECT) When SW_CONTROL = 1 this bit is reset to 0.

This bit controls whether CHRG_DET pin is controlled automatically or manually. When manual control is required, the software must set the SW_CONTROL bit to logic 1 in the first register access, followed by issuing a second register access to set or clear the HWDETECT bit. Software must never set the SW_CONTROL bit and change the HWDETECT bit in the same register access.

0b: The CHRG_DET pin will be asserted or deasserted depending on the automatic USB charger detection result.

1b: At rising-edge of SW_CONTROL bit save current hardware charger detection context and hand-off control to software:

1. DP_VSRC_EN register bit is loaded with current status of VDP_SRC
2. HWDETECT register bit is loaded with current status of charger detection result. Therefore battery charger indication signal to external charger remains unchanged.
3. Charger detection circuitry is maintained enabled if it was enabled in dead-battery condition
4. Charger Detection FSM is exited (to state USB_DET_OFF)
5. Control of POWER_CONTROL register bits is handed over to software

Therefore if charger detection has been initiated in dead-battery condition (while the chip is disabled (CS=0)), VDP_SRC will remain enabled and CHRG_DET pin status will not change when SW takes control, and SW can read register status before deciding to perform further charger/device/accessory detection or USB attach The CHRG_DET pin will be asserted or deasserted depending on the HWDETECT bit setting.

Control data polarity on DP/DM

DATAPOLARITY bit will control both DP/DM polarity in USB PHY and Charger Detection polarity in active mode but not charger detection in polarity in dead battery condition.

0b: DP & DM polarity is swapped

DP is mapped to C1 pin, DM mapped to D1 pin

1b: DP & DM polarity is not swapped

DP is mapped to D1 pin, DM mapped to C1 pin as described in Terminal description chapter

High speed output impedance configuration for eye diagram tuning :

00 45.455 Ω

01 43.779 Ω

10 42.793 Ω

11 42.411 Ω

High speed output drive strength configuration for eye diagram tuning :

0000 17.928 mA

0001 18.117 mA

0010 18.306 mA

0011 18.495 mA

0100 18.683 mA

0101 18.872 mA

0110 19.061 mA

0111 19.249 mA

1000 19.438 mA

1001 19.627 mA

1010 19.816 mA

1011 20.004 mA

1100 20.193 mA

1101 20.382 mA

1110 20.570 mA

1111 20.759 mA

IHSTX[0] is also the AC BOOST enable

IHSTX[0] = 0 → AC BOOST is disabled

IHSTX[0] = 1 → AC BOOST is enabled

It is the same as VENDOR_SPECIFIC1 register with read/set-only property (write '1' to set a particular bit, a write '0' has no-action).

It is the same as the VENDOR_SPECIFIC1 register with read/clear-only property (write '1' to clear a particular bit, a write '0' has no-action).

Current value of REG3V3IN_MNTR comparator

0: VBAT REG3V3IN_MNTR threshold

1: VBAT REG3V3IN_MNTR threshold

ACA Detection status output

00: ACA not detected

01: R_ID_A resistance on ID detected

10: R_ID_B resistance on ID detected

11: R_ID_C resistance on ID detected

The PHY follows the rules defined in Table 26 of the ULPI spec for setting any latch register bit.

_{Set according to table below when an unmasked event occurs on ACA Detection status output}

_{00: No ACA event detected}

_{01: ACA event. Detected}

_{10: ACA event. Detected}

_{11: ACA event. Detected}

This bit is used modify VBUS resistance to ground.

0: A-Device VBUS resistor RVBUS_IDLE_A is disabled. VBUS resistance to ground becomes RVBUS_IDLE_B (see Section 4.18)

1: A-Device VBUS resistor RVBUS_IDLE_A is enabled (see Section 4.18)

This bit is used to indicate to TUSB1211 whether an external series 1kohm resistor is connected on VBUS. When this bit is set internal VBUS comparator thresholds are adjusted so they remain in spec.

0: No external series resistor on VBUS

1: An external 1=kΩ series resistor is connected on VBUS

This bit controls PSW pin configuration. It can be overridden by PSW_CMOS bit below

‘0’: PSW pad is in OS mode (active high)

‘1’: PSW pad is in OD mode (active low)

This bit controls PSW pin configuration. It overrides PSW_OSOD bit above.

‘0’ : PSW pad is in OD or OS mode (controlled by PSW_OD bit)

‘1’: PSW pad is in CMOS mode

Read-only status bit showing status of debounced charger detection single-ended receiver comparator on DP

0: VDP < [0.8V : 2.0V] SERX threshold

1: VDP > [0.8V : 2.0V] SERX threshold

Note: This comparator and status bit is enabled automatically in the following scenarios:

• When charger detection FSM is enabled and VDP_SRC or IDP_SRC are enabled by FSM
• When SW_CONTROL=1 and DP_VSRC_EN =1
• When SW_CONTROL=1 and CHGD_IDP_SRC_EN=1
• When DP_WKPU_EN bit is enabled

In all other cases (including when DP 1.5K pullup is enabled by SW for CDP/DCP/SDP differentiation after SW charger detection step) this status bit should be ignored and LINESTATE<1:0> bits in DEBUG register, or RXCMD should be used for DP/DM detection

Read-only status bit showing status of debounced charger detection single-ended receiver comparator on DM

0: VDM < [0.8V : 2.0V] SERX threshold

1: VDM > [0.8V : 2.0V] SERX threshold

Note: This comparator and status bit is enabled automatically in the following scenarios:

• When charger detection FSM is enabled and VDP_SRC or IDP_SRC are enabled by FSM
• When SW_CONTROL=1 and DP_VSRC_EN =1
• When SW_CONTROL=1 and CHGD_IDP_SRC_EN=1
• When DP_WKPU_EN bit is enabled

In all other cases (including when DP 1.5K pullup is enabled by SW for CDP/DCP/SDP differentiation after SW charger detection step) this status bit should be ignored and LINESTATE<1:0> bits in DEBUG register, or RXCMD should be used for DP/DM detection

Autoresume watchdog timer enable bit

0b: Disable the Autoresume watchdog timer

1b: Enable the Autoresume watchdog timer

Timer is be initialized and starts counting when the PHY detects a resume-K.

When set to ‘1’, this bit enables RX CMD’s for high to low or low to high transitions on detection of ACA resistors RID_A , RID_B or RID_C .

When this bit is set to ‘1’ and any of the above ACA resistors are detected, TUSB1211 will send an RX CMD to the link with the alt_int bit set to 1b.

The status of ACA detection can then be read back through status bits ID_RARBRC_STS <1:0> Setting this bit also forces ID pull-up (RID_UP) to be enabled irrespective of IDPULLUP bit setting

Optional feature which can be used to indicate to Link if VBAT level is high enough to guarantee USB functionality

0b: Disable this monitoring featue

1b: Enable monitoring of REG3V3IN (=VBAT) level through RXCMD on detection of high to low or low to high transitions on comparator REG3V3IN_MNTR after debounce.

This bit is used to enable correct configuration of TUSB1211 as a B-device with ACA connected and nothing (or A-device OFF) at ACA Accessory port and charger present on ACA Charger Port, if ACA RID_B is detected on ID pin. It impacts:

a) VA_VBUS_VLD in RX CMD

b) VSESS_VLD in RX CMD

c) VBUS SRP

When this bit is‘1’ and RID_B is detected on ID pin , then mask VBUS plug detection information from being sent to the link, and mask OTG VBUS SRP commands (CHRGVBUS, DISCHRGVBUS bits) from the link. Set VA_VBUS_VLD =0 and VSESS_VLD =0 in RX CMD, and disable RB_SRP_UP, RB_SRP_DWN

Note: CHRGVBUS, DISCHRGVBUS register bit settings themselves are unchanged but VBUS SRP pullup and pulldown are disabled.

When this bit is ‘0’ RID_B detection has no impact on VA_VBUS_VLD detection and VA_SESS_VLD detection in RX CMD

This bit is used to enable correct configuration of TUSB1211 as an A-device with ACA connected and B-device at ACA Accessory port and charger connected to Charger Port , if ACA RID_A is detected on ID pin. It impacts:

a) IDGND detection in RXCMD and

b) Enabling of external VBUS on PSW pin

When this bit is ‘1’ and RID_A is detected on ID pin then TUSB1211 will be configured as an A-device by set ID=0 in RXCMD (equivalent to IDGND detected). In addition PSW pin is deasserted to avoid contention on VBUS pin since the charger at ACA port already provides VBUS.

When this bit is ‘0’ RID_A detection has no impact on RXCMD nor PSW pin

USB HS Start-of-Frame clock output feature enable

0: Disable HS SOF clock

1: Enable HS SOF clock output on SOF pin

HS USB SOF packet rate is 8kHz