SLLSE80B March 2011 – June 2015 TUSB1211
PRODUCTION DATA.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VBAT(3) | Main battery supply voltage | Continuous | 0 | 5.0 | V |
Main battery supply voltage pulsed | The product will have negligible reliability impact for pulsed voltage spikes of 5.5 V for a total (cumulative over lifetime) duration of 5 milliseconds | 5.5 | V | ||
VDDIO | IO supply voltage | Continuous | 1.98 | V | |
Voltage on any input except VDDIO, VBAT, and VBUS pads | Where VDD represents the voltage applied to the power supply pin associated with the input | –0.3 | 1.0 × VDD + 0.3 | V | |
DP, DM, ID high voltage short circuit | DP or DM or ID pins short-circuited to VBUS supply, in any mode of TUSB1211 operation, continuously for 24 hours | 5.25 | V | ||
DP, DM, ID low voltage short circuit | DP or DM or ID pins short-circuited to GND in any mode of TUSB1211 operation, continuously for 24 hours | 0 | V | ||
VBUS input(2) | –2 | 20 | V | ||
TA | Ambient temperature | –40 | 85 | °C | |
TJ | Junction temperature | –40 | 150 | °C | |
Tstg | Storage temperature | –55 | 125 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
VBAT | Battery supply voltage | VBAT_ACTIVE | 2.7 | 3.6 | 4.8 | V |
VBAT_CERT | Battery supply voltage for USB 2.0 compliancy (USB 2.0 certification) | When VDD33 is supplied internally | 3.15 | V | ||
When VDD33 is shorted to VBAT externally | 3.05 | |||||
VBAT_DB | Battery supply voltage for charger detect in “dead-battery condition” | VBAT_DB | 2.4 | V | ||
VDDIO | IO supply voltage | VDDIO_ACTIVE | 1.62 | 1.8 | 1.95 | V |
TA | Ambient temperature range | –40 | 85 | °C | ||
TJ | Junction temperature | For parametric compliance | –40 | 125 | °C |
MODE | CONDITIONS | SUPPLY | TYPICAL POWER CONSUMPTION |
UNIT |
---|---|---|---|---|
OFF | VBAT = 3.6 V, VDDIO = 1.8 V, CS = 0 V |
IVBAT | 8 | µA |
IVDDIO | 1.8 | |||
ITOTAL | 9.8 | |||
Suspend | VBUS = 5 V, VBAT = 3.6 V, VDDIO = 1.8 V, VCHRG_EN_N = 0 V, no clock |
IVBAT | 251 | µA |
IVDDIO | 21 | |||
ITOTAL | 272 | |||
HS USB Mode | VBAT = 3.6 V, VDDIO = 1.8 V, active USB transfer |
IVBAT | 46.4 | mA |
IVDDIO | 1.3 | |||
ITOTAL | 47.7 | |||
FS USB Mode | VBAT = 3.6 V, VDDIO = 1.8 V, active USB transfer |
IVBAT | 31.4 | mA |
IVDDIO | 1.3 | |||
ITOTAL | 32.7 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CHRG_EN_N INPUT PIN | ||||||
VILCDETENN | CHRG_EN_N maximum low-level input voltage | 0.3 | V | |||
VIHCDETENN | CHRG_EN_N minimum high-level input voltage | 1.0 | V | |||
CHRG_POL INPUT PIN | ||||||
VILCHRG_POL | CHRG_POL maximum low-level input voltage | 0.3 | V | |||
VIHCHRG_POL | CHRG_POL minimum high-level input voltage | 1.0 | V | |||
FAULT INPUT PIN | ||||||
VILFAULT | FAULT maximum low-level input voltage | 0.3 | V | |||
VIHFAULT | FAULT minimum high-level input voltage | 1.0 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CLOCK | ||||||
VOL | Low-level input voltage | Frequency = 60 MHz, Load = 10 pF | 0.4 | V | ||
VOH | High-level input voltage | VDDIO – 0.45 | V | |||
STP, DIR, NXT, DATA0 to DATA7 | ||||||
VOL | Low-level input voltage | Frequency = 360 MHz, Load = 10 pF | 0.45 | V | ||
VOH | High-level input voltage | VDDIO – 0.45 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CS, CFG, RESETB INPUT PINS | ||||||
VIL | Maximum low-level input voltage | 0.35 × VDDIO | V | |||
VIH | Minimum high-level input voltage | 0.65 × VDDIO | V | |||
RESET_N INPUT PIN TIMING SPECIFICATION | ||||||
tw(POR) | Internal power-on reset pulse width | 0.2 | µs | |||
tw(RESET) | External RESET_N pulse width | Applied to external RESET_N pin when CLOCK is toggling. | 8 | CLOCK cycles |
PARAMETER | TEST CONDITIONS | MIN(1) | TYP | MAX(1) | UNIT | |
---|---|---|---|---|---|---|
VIL | Low level input voltage | 0.35 × VDDIO | V | |||
VIH | High level input voltage | 0.65 × VDDIO | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
CLOCK input duty cycle | 40% | 60% | |||
FCLOCK CLOCK nominal frequency | 60 | MHz | |||
CLOCK input rise/fall time | In % of CLOCK period TCLOCK ( = 1/FCLOCK ) | 10% | |||
CLOCK input frequency accuracy | 250 | ppm | |||
CLOCK input integrated jitter | 600 | ps rms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
REFCLK input duty cycle | 40% | 60% | |||
FREFCLK REFCLK nominal frequency | When CFG pin is tied to GND | 19.2 | MHz | ||
When CFG pin is tied to VDDIO | 26 | ||||
REFCLK input rise/fall time | In % of REFCLK period TREFCLK ( = 1/FREFCLK ) | 20% | |||
REFCLK input freq accuracy | 250 | ppm | |||
REFCLK input integrated jitter | 600 | ps rms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Output duty cycle | 48% | 50% | 52% | ||
Output frequency | 23 | 32.7 | 38 | kHz |
THERMAL METRIC(1) | TUSB1211 | UNIT | |
---|---|---|---|
ZRQ (BGA MICROSTAR JUNIOR) | |||
36 PINS | |||
RθJA | Junction-to-ambient thermal resistance(2) | 69.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance(3)(4) | 41 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance(4)(5) | N/A | °C/W |
RθJB | Junction-to-board thermal resistance or junction-to-pin thermal resistance(6) | 42 | °C/W |
ΨJT | Junction-to-top of package (not a true thermal resistance)(7) | 0.9 | °C/W |
ΨJB | Junction-to-board (not a true thermal resistance)(8) | 71 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VINREG3V3 | Input voltage | VBAT | VOUT(typ) + 0.15 | 3.6 | 4.8 | V |
VVDD33 | Output voltage ACTIVE mode |
On mode – REG3V3_VSEL<2:0> = ‘000 | 2.4 | 2.5 | 2.6 | V |
On mode – REG3V3_VSEL<2:0> = ‘001 | 2.65 | 2.75 | 2.85 | |||
On mode – REG3V3_VSEL<2:0> = ‘010 | 2.9 | 3. | 3.1 | |||
On mode – REG3V3_VSEL<2:0> = ‘011 (default) | 3 | 3.1 | 3.2 | |||
On mode – REG3V3_VSEL<2:0> = ‘100 | 3.1 | 3.2 | 3.3 | |||
On mode – REG3V3_VSEL<2:0> = ‘101 | 3.2 | 3.3 | 3.4 | |||
On mode – REG3V3_VSEL<2:0> = ‘110 | 3.3 | 3.4 | 3.5 | |||
On mode – REG3V3_VSEL<2:0> = ‘111 | 3.4 | 3.5 | 3.6 | |||
VVDD33_DB | Output voltage hardware charger detection (dead battery) mode |
VBAT_DB < VBAT < 3.1 V | VBAT – 0.05 | VBAT | VBAT + 0.05 | V |
VBAT > 3.1 V | 3 | 3.1 | 3.2 | |||
IREG3V3 | Rated output current | VBAT: ACTIVE mode, Hardware charger detection (dead battery) mode |
15 | mA | ||
IREG3V3_SUSP | Rated output current: IREG3V3_SUSP |
Suspend mode/reset mode | 1 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VINREG1V8 | Input voltage | On mode : VINREG1V8 = VBAT | 2.4 | 3.6 | 4.8 | V |
VREG1V8 | Output voltage | 1.75 | 1.87 | 1.98 | V | |
IREG1V8 | Rated output current | On mode | 30 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VINREG1V8 | Input voltage | On mode : VINREG1V8 = VBAT | 2.4 | 3.6 | 4.8 | V |
VREG1V8 | Output voltage | 1.45 | 1.56 | 1.65 | V | |
IREG1V8 | Rated output current | On mode | 50 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
USB SINGLE-ENDED RECEIVERS | ||||||
SKWVP_VM | Skew between VP and VM | Driver outputs unloaded | –2 | 0 | 2 | ns |
VSE_HYS | Single-ended hysteresis | 50 | mV | |||
VIH | High (driven) | 2 | V | |||
VIL | Low | 0.8 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VDI | Differential Input Sensitivity | Ref. USB2.0 | 200 | mV | ||
VCM | Differential Common Mode Range | Ref. USB2.0 | 0.8 | 2.5 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOL | Low | Ref. USB2.0 | 0 | 300 | mV | |
VOH | High (driven) | Ref. USB2.0 | 2.8 | 3.6 | V | |
VCRS | Output signal crossover voltage | Ref. USB2.0 | 1.3 | 2 | V | |
TFR | Rise time | Ref. USB2.0, covered by eye diagram |
75 | 300 | ns | |
TFF | Fall time | Ref. USB2.0, covered by eye diagram |
75 | 300 | ns | |
TFRFM | Differential rise and fall time matching | 80% | 125% | |||
TFDRATE | Low-speed data rate | 1.4775 | 1.5225 | Mb/s | ||
Total source jitter (including frequency tolerance): |
Ref. USB2.0, covered by eye diagram | |||||
TDJ1 | To next transition | –25 | 25 | ns | ||
TDJ2 | For paired transitions | –10 | 10 | |||
TFEOPT | Source SE0 interval of EOP | Ref. USB2.0, covered by eye diagram |
1.25 | 1.5 | µs | |
Downstream eye diagram | Ref. USB2.0, covered by eye diagram |
|||||
VCM | Differential common mode range | Ref. USB2.0 | 0.8 | 2.5 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOL | Low | Ref. USB2.0 | 0 | 300 | mV | |
VOH | High (driven) | Ref. USB2.0 | 2.8 | 3.6 | V | |
VCRS | Output signal crossover voltage | Ref. USB2.0 | 1.3 | 2 | V | |
TFR | Rise time | Ref. USB2.0, covered by eye diagram |
4 | 20 | ns | |
TFF | Fall time | Ref. USB2.0 | 4 | 20 | ns | |
TFRFM | Differential rise and fall time matching | Ref. USB2.0, covered by eye diagram |
90% | 111.11% | ||
ZDRV | Driver output resistance | Ref. USB2.0 | 28 | 44 | Ω | |
TFDRATE | Full-speed data rate | Ref. USB2.0, covered by eye diagram |
11.97 | 12.03 | Mb/s | |
Total source jitter (including frequency tolerance): |
Ref. USB2.0, covered by eye diagram |
|||||
TDJ1 | To next transition | –2 | 2 | ns | ||
TDJ2 | For paired transitions | –1 | 1 | |||
TFEOPT | Source SE0 interval of EOP | Ref. USB2.0, covered by eye diagram |
160 | 175 | ns | |
Downstream eye diagram | Ref. USB2.0, covered by eye diagram |
|||||
Upstream eye diagram |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VHSOI | High-speed idle level | Ref. USB2.0 | –10 | 10 | mV | |
VHSOH | High-speed data signaling high | Ref. USB2.0 | 360 | 440 | mV | |
VHSOL | High-speed data signaling low | Ref. USB2.0 | –10 | 10 | mV | |
VCHIRPJ | Chirp J level (differential voltage) | Ref. USB2.0 | 700 | 1100 | mV | |
VCHIRPK | Chirp K level (differential voltage) | Ref. USB2.0 | –825 | –500 | mV | |
THSR | Rise time (10% to 90%) | Ref. USB2.0, covered by eye diagram | 500 | ps | ||
Fall time (10% to 90%) | 500 | |||||
ZHSDRV | Driver output resistance (which also serves as high-speed termination) |
Ref. USB2.0 | 40.5 | 49.5 | Ω | |
THSDRAT | High-speed data range | Ref. USB2.0, covered by eye diagram | 479.76 | 480.24 | Mb/s | |
Data source jitter | Ref. USB2.0, covered by eye diagram | |||||
Downstream eye diagram | Ref. USB2.0, covered by eye diagram | |||||
Upstream eye diagram | Ref. USB2.0, covered by eye diagram |
PARAMETER | NB CK32K cycles | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
TAUTORESUME | Autoresume time-out | 918 | 20.0 | 28.0 | 46.7 | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ISUSP
(USB BC Ver1.1 spec) |
VBUS maximum current in dead battery. Maximum current the device is allowed to draw from VBUS in dead battery condition if VDP_SRC is not asserted | Averaged over 1 s | 1 | mA | ||
IVBAT_DET | VBAT maximum current during battery charger detection | 450 | 550 | µA | ||
IDP_SRC | Data contact detect current source | 7 | 13 | µA | ||
IDM_SINK | DM sink current | 50 | 150 | µA | ||
IDEV_HCHG_CHRP | Portable device current from charging downstream port during chirp | Refer to USB Battery Charging spec V1.1 Ch6.3.2 and values of VHSCM, and VCHIRPK | 710 | mA | ||
IVDP_SRC_ILIM | DP voltage source current limitation | VDP = 0 V | 800 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RDP_DWN | DP pulldown resistance | 14.25 | 24.8 | kΩ | ||
RDM_DWN | DP pulldown resistance | 14.25 | 24.8 | kΩ | ||
RDCHG_DAT | Dedicated charging port resistance across DP/DM (input spec to TUSB1211) | 200 | Ω | |||
RDCHRGR_PWR | Dedicated charging port resistance from DP/DM to VBUS/GND (input spec to TUSB1211) | 2 | MΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CDCHG_PWR | Dedicated charging port capacitance from DP or DP to VBUS or GND (input spec to TUSB1211) | 1 | nF |
PARAMETER | NB CK32K CYCLES | TEST CONDITIONS | BC1.1 SPEC |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|---|
DEBVBUS_TIME | VBUS debounce time | 459 | > 10 | 12.1 | 14.0 | 20.0 | ms | |
TIDP_SRC_ON | DP Current source on-time | 8 | > 200 | 210.5 | 244.1 | 347.8 | µA | |
TVDP_SRC_ON | DP Voltage source on-time | 1792 | > 40 | 47.2 | 54.7 | 77.9 | ms | |
TVDP_SRC_HICRNT | DP Voltage source off to high current on charger delay | 1792 | > 40 | 47.2 | 54.7 | 77.9 | ms | |
TDCD_TIMEOUT | Data contact detect timeout | 89400 | > 2 | 2.4 | 2.7 | 3.9 | s | |
TSVLD_CON_WKB | Session valid to connect for peripheral with dead or weak battery | 53084160 | Used to generate SVLDCONWKB_CNTR in FSM | < 45 | 27.0 | 23.3 | 38.5 | min |
TVDPSRC_CON | DP voltage source off to connect delay | N/A | Input spec | > 40 | N/A | N/A | N/A | ms |
TVDPSRC_DEB | VDP_SRC comparator debounce time | 760 | Used to generate CHGD_VDM_DEB in FSM | N/A | 20.0 | 23.2 | 33.0 | ms |
TCHGD_SERX_DEB | Charger detect SERX debounce time | 1520 | Used to generate CHGD_SERX_DP_DEB and CHGD_SERX_DM_DEB in FSM | N/A | 40.0 | 46.4 | 66.1 | ms |
TACA_SETUP | ACA setup time | 2300 | N/A | 60.5 | 70.2 | 100.0 | ms | |
TID_RARBRC_DEB | ACA ID RA, RB, RC comparators debounce | 1520 | Used to generate ID_RARBRC_DEB in FSM | N/A | 40.0 | 46.4 | 66.1 | ms |
This scenario corresponds to standard power-up of TUSB1211 device in presence of valid VBAT, VIO, and chip selected (CS = 1 and CS_N = 0).
A timing diagram for standard power up is shown in Figure 4-1. In this plot USB ULPI clock is configured in output mode. A suggested application diagram for this configuration is shown in Section 6.
NOTE
The ULPI clock can also be configured in input mode, see Figure 4-1 for details.
This scenario corresponds to “dead battery” scenario in USB Battery Charging Specification V1.1.
Here VBUS is plugged while chip is not enabled (CS = 0 or CS_N = 1 or both), with VBAT > VBAT_DET. This causes the device to power up to and initiate Charger Detection through hardware. See Section 5.3.12 for details.
The USB PLL block generates the clocks used to synchronize:
TUSB1211 requires an external reference clock which is used as an input to the 480MHz USB PLL block. Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at CLOCK pin.
By default CLOCK pin is configured as an input.
Two clock configurations are possible:
In this mode REFCLK must be externally tied to GND.
CLOCK remains configured as an input.
When the ULPI interface is used in “input clock configuration”, that is, the 60 MHz ULPI clock is provided to TUSB1211 on CLOCK pin, then this is used as the reference clock for the 480 MHz USB PLL block.
In this mode a reference clock must be externally provided on REFCLK pin.
When an input clock is detected on REFCLK pin then CLOCK will automatically change to an output, that is, 60 MHz ULPI clock is output by TUSB1211 on CLOCK pin.
Two reference clock input frequencies are supported. REFCLK input frequency is communicated to TUSB1211 through a configuration pin, CFG, see FREFCLK in Section 4.11 for frequency correspondence.
TUSB1211 supports square-wave reference clock input only.
This chapter describes the electrical characteristics of the voltage regulators and timing characteristics of the supplies digitally controlled within the TUSB1211 device.
SUPPLY NAME | PIN NAME | TYPE | TYPICAL VOLTAGE (V) |
---|---|---|---|
REG1V5 | REG1V5 | LDO | 1.5 |
REG1V8 | — | LDO | 1.8 |
REG3V3 | REG3V3 | LDO | 3.1 |
LDO NAME | PIN NAME | USAGE | TYPE | TYPICAL VOLTAGE (V) | MAXIMUM CURRENT |
---|---|---|---|---|---|
REG1V5 | REG1V5 | Internal | LDO | 1.5 | 50 mA |
REG1V8 | — | Internal (capless) | LDO | 1.8 | 30 mA |
REG3V3 | REG3V3 | Internal | LDO | 3.1 | 15 mA |
The REG3V3 internal LDO regulator powers the USB PHY, Charger detection, and OTG functions of the USB subchip inside TUSB1211.
It takes its power from the VBAT pin. It is connected to an external filtering capacitor at the REG3V3 pin (E3).
The USB standard requires data lines to be biased with pullups powered from a >3.0 V supply. Hence TUSB1211 cannot be guaranteed USB2.0 compliant for VBAT voltage lower than VBAT_CERT. TUSB1211 will however keep operating below this voltage.
The REG1V8 internal LDO regulator powers the USB PHY, and USB PLL.
It takes its power from the VBAT pin. This LDO is capless, that is, its output is not connected to any external pin.
Section 4.15 describes its characteristics.
The REG1V5 internal LDO regulator powers the USB PHY and internal digital circuitry of TUSB1211. Section 4.16 describes the regulator characteristics.
It takes its power from the VBAT pin. It is connected to an external filtering capacitor at the REG1V5 pin (E6).
TUSB1211 can be powered up in two different modes:
For this, VBAT and VIO must be present and chip must be selected (CS=1 and CS_N=0). See Section 4.33.1. Standard Power-up Timing Power resources will be configured sequentially until the device reaches the power state.
USBON . At this time internal power-on-reset signal PORZ will be released and USB PLL will start up. Once PLL is locked, the DIR output pin will be deasserted allowing TUSB1211 to be configured by the USB Link Controller through the ULPI interface.
Note that by default TUSB1211 will be configured as a Host not providing VBUS as required by register map in ULPI specification Rev1.1.
This is the case because OTG_CONTROL register bits DRVVBUS and DRVVBUSEXTERNAL bits are 0 by default, and DPPULLDOWN, DMPULLDOWN bits are 1 by default such that the 15 kΩ pulldown resistors at DP/DM pins are enabled by default.
It is the responsibility of the link to enable external VBUS supply if required in Host mode, or to reconfigure the PHY if required in Device mode.
When the chip is not selected (CS=0 or CS_N=1), but VBUS is present and CHRG_EN_N pin is at GND, and VBAT > VBAT_MNTR then TUSB1211 will power-up in Hardware Charger Detection Mode.
Power resources will be configured sequentially until the device reaches the power state USBON. However, because the chip is not selected, the internal power-on-reset signal PORZ will be not be released and USB PLL will not start up. Instead the device will enter the USB battery charger finite state machine (FSM) .