SLLSE80B March 2011 – June 2015 TUSB1211
PRODUCTION DATA.
NO. | PIN(1) | NAME | A/D(2) | TYPE(3) | LEVEL(4) | DESCRIPTION |
---|---|---|---|---|---|---|
1 | D5 | NXT | D | O | VDDIO | ULPI NXT output signal |
2 | B1 | DATA0 | D | I/O | VDDIO | ULPI DATA input/output signal synchronized to CLOCK |
3 | A1 | DATA1 | D | I/O | VDDIO | ULPI DATA input/output signal synchronized to CLOCK |
4 | A2 | DATA2 | D | I/O | VDDIO | ULPI DATA input/output signal synchronized to CLOCK |
5 | A3 | DATA3 | D | I/O | VDDIO | ULPI DATA input/output signal synchronized to CLOCK |
6 | A5 | DATA4 | D | I/O | VDDIO | ULPI DATA input/output signal synchronized to CLOCK |
7 | A6 | DATA5 | D | I/O | VDDIO | ULPI DATA input/output signal synchronized to CLOCK |
8 | B6 | DATA6 | D | I/O | VDDIO | ULPI DATA input/output signal synchronized to CLOCK |
9 | B3 | CS | D | I | VDDIO | Active-high chip select pin. When low the IC is in power down and ULPI bus is tri-stated. When high (and CS_N pin iTie to VDDIO if unused.s low) normal operation. |
10 | E6 | REG1V5 | A | POWER | VDD15 | 1.5 V internal LDO output. Connect to external filtering capacitor. |
11 | C6 | DATA7 | D | I/O | VDDIO | ULPI DATA input/output signal synchronized to CLOCK |
12 | B4 | CFG | D | I | VDDIO | REFCLK clock frequency configuration pin. Two frequencies are supported: 19.2 MHz when 0, or 26 MHz when 1. |
13 | D1 | DP | A | I/O | VDD33 | DP pin of the USB connector |
14 | C1 | DM | A | I/O | VDD33 | DM pin of the USB connector |
15 | E3 | REG3V3 | A | POWER | VDD33 | 3.3 V internal LDO output. Connect to external filtering capacitor. |
16 | F3 | VBAT | A | POWER | VBAT | Input supply voltage or battery source. Nominally 3.3 V to 4.5 V |
17 | F4 | VBUS | A | I/O | VBUS | VBUS pin of the USB connector |
18 | D3 | ID | A | I/O | VBUS | Identification (ID) pin of the USB connector |
19 | A4 | CLOCK | D | I/O | VDDIO | ULPI 60-MHz clock on which ULPI data is synchronized. 2 modes are possible: Input Mode: CLOCK defaults as an input (this is the default clock mode) Output Mode: When an input clock is detected on REFCLK pin then CLOCK will change to an output |
20 | C4 | RESET_N | D | I | VDDIO | Active low chip reset pin. Minimum pulse width 100 µs. When low all digital logic (except 32-kHz logic required for power-up sequencing and charger detection state-machine) including registers are reset to their default values. ULPI bus is in “ULPI Synchronous mode power-up PLL OFF” state as described in Table 5-5. When high normal USB operation. |
21 | D6 | STP | D | I | VDDIO | ULPI STP input signal |
22 | E5 | DIR | D | O | VDDIO | ULPI DIR output signal |
23 | B5 | VDDIO | A | I | VDDIO | External 1.8-V supply input for digital I/Os. Connect to external filtering capacitor. |
24 | B2 | VDDIO | A | I | VDDIO | External 1.8-V supply input for digital I/Os. Connect to external filtering capacitor. |
25 | C5 | GND | A | GROUND | GND | Ground |
26 | D2 | GND | A | GROUND | GND | Ground |
27 | E4 | GND | A | GROUND | GND | Ground |
28 | F5 | REFCLK | D | I | VDDIO | Reference clock input. Input reference clock frequency must be indicated by CFG pin. Two frequencies are supported: 19.2 MHz (when CFG = 0), and 26 MHz (when CFG = 1). |
29 | F6 | SOF | D | O | VDDIO | HS USB SOF (Start-of-Frame) output clock. (feature controlled by SOF_EN bit, disabled and output logic low by default.). HS USB SOF packet rate is 8 kHz. |
30 | C2 | NC | — | — | Not connected | |
31 | C3 | CS_N | D | I | VDDIO | Active-low chip select pin. When high the IC is in power down and ULPI bus is tri-stated. When low (and CS pin is high) normal operation. Tie to GND if unused. |
32 | E1 | CHRG_EN_N | D | I | VBAT | Active low input pin used to enable Battery Charging Detection in Dead Battery Charger Detection mode. This pin is ignored in ACTIVE mode. Connect to GND to activate. Connect to VBAT when charger detection not required. |
33 | E2 | FAULT | D | I | VBAT | VBUS fault detector input used as EXTERNALVBUSINDICATOR in TUSB1211. The link must enable VBUS fault detection through the USEEXTERNALVBUSINDICATOR register bit, and the polarity must be set through the INDICATORCOMPLEMENT register bit. INDICATORPASSTHRU bit can be used to qualify FAULT with the internal vbusvalid comparator. Connect to GND if not used. This pin is 5-V tolerant. |
34 | F1 | CHRG_POL | D | I | VBAT | When connected to GND then CHRG_DET output pin is active low. When connected to VBAT then CHRG_DET output pin is active high. |
35 | F2 | CHRG_DET | D | O | VBAT | When CHRG_POL pin is at GND then CHRG_DET is in active low open-drain mode with external RCHRGDET (100K) connected to VBAT. When CHRG_POL pin is at VBAT then CHRG_DET is in active high open-source mode with external RCHRGDET (100K) connected to GND. This pin is 5-V tolerant. |
36 | D4 | PSW | D | O | VBAT | Controls an external, active high, VBUS power switch or charge pump. Open source output on VBAT supply when PSW_OSOD bit is 0 (default), open-drain active-low output when PSW_OSOD bit is 1. Requires an external RPSW (100K) pulldown/pullup resistor to GND/VBAT. |