SLLSE80B March   2011  – June 2015 TUSB1211

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagram
      1. 3.1.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Power Consumption Summary
    5. 4.5  Electrical Characteristics - Analog Output Pins
    6. 4.6  Electrical Characteristics - Analog Input Pins
    7. 4.7  Digital I/O Electrical Characteristics - Non-ULPI Pins
    8. 4.8  Digital I/O Electrical Characteristics - Non-ULPI Pins
    9. 4.9  Electrical Characteristics - REFCLK
    10. 4.10 Electrical Characteristics - CLOCK Input
    11. 4.11 Electrical Characteristics - REFCLK
    12. 4.12 Electrical Characteristics - CK32K Clock Generator
    13. 4.13 Thermal Characteristics
    14. 4.14 REG3V3 Internal LDO Regulator Characteristics
    15. 4.15 REG1V8 Internal LDO Regulator Characteristics
    16. 4.16 REG1V5 Internal LDO Regulator Characteristics
    17. 4.17 Timers and Debounce
    18. 4.18 OTG VBUS Electrical
    19. 4.19 LS/FS Single-Ended Receivers
    20. 4.20 LS/FS Differential Receiver
    21. 4.21 LS Transmitter
    22. 4.22 FS Transmitter
    23. 4.23 HS Transmitter
    24. 4.24 Pullup and Pulldown Resistors
    25. 4.25 Autoresume Watchdog Timer
    26. 4.26 UART Transceiver
    27. 4.27 OTG ID Electrical
    28. 4.28 Electrical Specs - Charger Detection Currents
    29. 4.29 Electrical Specs - Resistance
    30. 4.30 Electrical Specs - Capacitance
    31. 4.31 Charger Detection Debounce and Wait Timing
    32. 4.32 ULPI Interface
      1. 4.32.1 ULPI Interface Timing
    33. 4.33 Power-On Timing Diagrams
      1. 4.33.1 Standard Power-up Timing
      2. 4.33.2 Hardware Charger Detection Power-Up Timing
    34. 4.34 Clock System
      1. 4.34.1 USB PLL Reference Clock
        1. 4.34.1.1 ULPI Input Clock Configuration
        2. 4.34.1.2 ULPI Output Clock Configuration
    35. 4.35 Clock System
      1. 4.35.1 Internal Clock Generator (32 kHz)
    36. 4.36 Power Management
      1. 4.36.1 Power Provider
    37. 4.37 Power Provider
      1. 4.37.1 REG3V3 Regulator
      2. 4.37.2 REG1V8 Regulator
      3. 4.37.3 REG1V5 Regulator
    38. 4.38 Power Control
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  USB On-The-Go (OTG) Feature
      2. 5.3.2  VBUS Detection Status Bits vs VBUS Comparators
      3. 5.3.3  USB Transceiver (PHY)
        1. 5.3.3.1 PHY Overview
      4. 5.3.4  LS/FS Single-Ended Receivers
      5. 5.3.5  LS/FS Differential Receiver
      6. 5.3.6  LS/FS Transmitter
      7. 5.3.7  HS Differential Receiver
      8. 5.3.8  HS Differential Transmitter
      9. 5.3.9  Autoresume
      10. 5.3.10 UART Transceiver
      11. 5.3.11 USB On-The-Go (OTG)
        1. 5.3.11.1 ID Detection Status Bits vs ID Comparators
      12. 5.3.12 USB Battery Charger Detection and ACA
      13. 5.3.13 USB Battery Charger Detection Modes
      14. 5.3.14 Accessory Charger Adapter (ACA) Detection
    4. 5.4 Register Maps
      1. 5.4.1  VENDOR_ID_LO
      2. 5.4.2  VENDOR_ID_HI
      3. 5.4.3  PRODUCT_ID_LO
      4. 5.4.4  PRODUCT_ID_HI
      5. 5.4.5  FUNC_CTRL
      6. 5.4.6  FUNC_CTRL_SET
      7. 5.4.7  FUNC_CTRL_CLR
      8. 5.4.8  IFC_CTRL
      9. 5.4.9  IFC_CTRL_SET
      10. 5.4.10 IFC_CTRL_CLR
      11. 5.4.11 OTG_CTRL
      12. 5.4.12 OTG_CTRL_SET
      13. 5.4.13 OTG_CTRL_CLR
      14. 5.4.14 USB_INT_EN_RISE
      15. 5.4.15 USB_INT_EN_RISE_SET
      16. 5.4.16 USB_INT_EN_RISE_CLR
      17. 5.4.17 USB_INT_EN_FALL
      18. 5.4.18 USB_INT_EN_FALL_SET
      19. 5.4.19 USB_INT_EN_FALL_CLR
      20. 5.4.20 USB_INT_STS
      21. 5.4.21 USB_INT_LATCH
      22. 5.4.22 DEBUG
      23. 5.4.23 SCRATCH_REG
      24. 5.4.24 SCRATCH_REG_SET
      25. 5.4.25 SCRATCH_REG_CLR
      26. 5.4.26 POWER_CONTROL
      27. 5.4.27 POWER_CONTROL_SET
      28. 5.4.28 POWER_CONTROL_CLR
      29. 5.4.29 VENDOR_SPECIFIC1
      30. 5.4.30 VENDOR_SPECIFIC1_SET
      31. 5.4.31 VENDOR_SPECIFIC1_CLR
      32. 5.4.32 VENDOR_SPECIFIC2_STS
      33. 5.4.33 VENDOR_SPECIFIC2_LATCH
      34. 5.4.34 VENDOR_SPECIFIC3
      35. 5.4.35 VENDOR_SPECIFIC3_SET
      36. 5.4.36 VENDOR_SPECIFIC3_CLR
      37. 5.4.37 VENDOR_SPECIFIC4
      38. 5.4.38 VENDOR_SPECIFIC4_SET
      39. 5.4.39 VENDOR_SPECIFIC4_CLR
      40. 5.4.40 VENDOR_SPECIFIC5
      41. 5.4.41 VENDOR_SPECIFIC5_SET
      42. 5.4.42 VENDOR_SPECIFIC5_CLR
      43. 5.4.43 VENDOR_SPECIFIC6
      44. 5.4.44 VENDOR_SPECIFIC6_SET
      45. 5.4.45 VENDOR_SPECIFIC6_CLR
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Unused Pins Connection
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Ground
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
      2. 7.1.2 Community Resources
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VBAT(3) Main battery supply voltage Continuous 0 5.0 V
Main battery supply voltage pulsed The product will have negligible reliability impact for pulsed voltage spikes of 5.5 V for a total (cumulative over lifetime) duration of 5 milliseconds 5.5 V
VDDIO IO supply voltage Continuous 1.98 V
Voltage on any input except VDDIO, VBAT, and VBUS pads Where VDD represents the voltage applied to the power supply pin associated with the input –0.3 1.0 × VDD + 0.3 V
DP, DM, ID high voltage short circuit DP or DM or ID pins short-circuited to VBUS supply, in any mode of TUSB1211 operation, continuously for 24 hours 5.25 V
DP, DM, ID low voltage short circuit DP or DM or ID pins short-circuited to GND in any mode of TUSB1211 operation, continuously for 24 hours 0 V
VBUS input(2) –2 20 V
TA Ambient temperature –40 85 °C
TJ Junction temperature –40 150 °C
Tstg Storage temperature –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.3 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If VBUS exceeds above rating an external voltage protection on the line is mandatory between the VBUS line and the TUSB1211.
(3) If VBAT exceeds above rating a device to drop down the voltage before applied to the device.

4.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VBAT Battery supply voltage VBAT_ACTIVE 2.7 3.6 4.8 V
VBAT_CERT Battery supply voltage for USB 2.0 compliancy (USB 2.0 certification) When VDD33 is supplied internally 3.15 V
When VDD33 is shorted to VBAT externally 3.05
VBAT_DB Battery supply voltage for charger detect in “dead-battery condition” VBAT_DB 2.4 V
VDDIO IO supply voltage VDDIO_ACTIVE 1.62 1.8 1.95 V
TA Ambient temperature range –40 85 °C
TJ Junction temperature For parametric compliance –40 125 °C

4.4 Power Consumption Summary(1)(2)

MODE CONDITIONS SUPPLY TYPICAL POWER
CONSUMPTION		 UNIT
OFF VBAT = 3.6 V, VDDIO = 1.8 V,
CS = 0 V		 IVBAT 8 µA
IVDDIO 1.8
ITOTAL 9.8
Suspend VBUS = 5 V, VBAT = 3.6 V,
VDDIO = 1.8 V, VCHRG_EN_N = 0 V,
no clock		 IVBAT 251 µA
IVDDIO 21
ITOTAL 272
HS USB Mode VBAT = 3.6 V, VDDIO = 1.8 V,
active USB transfer		 IVBAT 46.4 mA
IVDDIO 1.3
ITOTAL 47.7
FS USB Mode VBAT = 3.6 V, VDDIO = 1.8 V,
active USB transfer		 IVBAT 31.4 mA
IVDDIO 1.3
ITOTAL 32.7
(1) Describes the power consumption depending on the use cases.
(2) Typical power consumption is obtained in nominal operating conditions of the TUSB1211 device.

4.5 Electrical Characteristics – Analog Output Pins

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CHRG_DET OUTPUT PIN
RCDETPUOD CHRG_DET external pullup resistor to VBAT When CHRG_POL pin = GND, that is, in open-drain mode (active-low) 60 100 kΩ
VOHCDETOD CHRG_DET minimum high-level output voltage When CHRG_POL pin = GND, that is, in open-drain mode (active-low) 0.7 × VBAT V
IOHCDETOD CHRG_DET maximum current from VBAT When CHRG_POL pin = GND, that is, in open-drain mode (active-low) 2 mA
RCDETPDOS CHRG_DET external pulldown resistor to GND When CHRG_POL pin = VBAT, that is, in open-source mode (active-high) 60 100 kΩ
VOLCDETOS CHRG_DET maximum low-level output voltage When CHRG_POL pin = VBAT, that is, in open-source mode (active-high) 0.3 × VBAT V
IOHCDETOS CHRG_DET minimum current from VBAT When CHRG_POL pin = VBAT, that is, in open-source mode (active-high) –2 mA
PSW OUTPUT PIN
RPSWPUOD PSW external pullup resistor to VBAT When configured in open-drain active low mode 60 100 kΩ
VOHPSW PSW minimum high-level output voltage When configured in open-drain active low mode or CMOS mode 0.7 × VBAT V
IOHPSWOD PSW maximum current from VBAT When configured in open-drain active low mode 2 mA
RPSWPDOS PSW external pulldown resistor to ground When configured in open-source active high mode (default) 60 100 kΩ
VOLPSW PSW minimum high-level output voltage When configured in open-source active high mode (default) or CMOS mode 0.3 × VBAT V
IOHPSWOS PSW maximum current from VBAT When configured in open-source active high mode (default) –2 mA

4.6 Electrical Characteristics – Analog Input Pins

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CHRG_EN_N INPUT PIN
VILCDETENN CHRG_EN_N maximum low-level input voltage 0.3 V
VIHCDETENN CHRG_EN_N minimum high-level input voltage 1.0 V
CHRG_POL INPUT PIN
VILCHRG_POL CHRG_POL maximum low-level input voltage 0.3 V
VIHCHRG_POL CHRG_POL minimum high-level input voltage 1.0 V
FAULT INPUT PIN
VILFAULT FAULT maximum low-level input voltage 0.3 V
VIHFAULT FAULT minimum high-level input voltage 1.0 V

4.7 Digital I/O Electrical Characteristics – Non-ULPI Pins

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLOCK
VOL Low-level input voltage Frequency = 60 MHz, Load = 10 pF 0.4 V
VOH High-level input voltage VDDIO – 0.45 V
STP, DIR, NXT, DATA0 to DATA7
VOL Low-level input voltage Frequency = 360 MHz, Load = 10 pF 0.45 V
VOH High-level input voltage VDDIO – 0.45 V

4.8 Digital I/O Electrical Characteristics – Non-ULPI Pins

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CS, CFG, RESETB INPUT PINS
VIL Maximum low-level input voltage 0.35 × VDDIO V
VIH Minimum high-level input voltage 0.65 × VDDIO V
RESET_N INPUT PIN TIMING SPECIFICATION
tw(POR) Internal power-on reset pulse width 0.2 µs
tw(RESET) External RESET_N pulse width Applied to external RESET_N pin when CLOCK is toggling. 8 CLOCK cycles

4.9 Electrical Characteristics – REFCLK

PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT
VIL Low level input voltage 0.35 × VDDIO V
VIH High level input voltage 0.65 × VDDIO V
(1) VDDIO voltage level = 1.8 V

4.10 Electrical Characteristics – CLOCK Input

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLOCK input duty cycle 40% 60%
FCLOCK CLOCK nominal frequency 60 MHz
CLOCK input rise/fall time In % of CLOCK period TCLOCK ( = 1/FCLOCK ) 10%
CLOCK input frequency accuracy 250 ppm
CLOCK input integrated jitter 600 ps rms

4.11 Electrical Characteristics – REFCLK

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFCLK input duty cycle 40% 60%
FREFCLK REFCLK nominal frequency When CFG pin is tied to GND 19.2 MHz
When CFG pin is tied to VDDIO 26
REFCLK input rise/fall time In % of REFCLK period TREFCLK ( = 1/FREFCLK ) 20%
REFCLK input freq accuracy 250 ppm
REFCLK input integrated jitter 600 ps rms

4.12 Electrical Characteristics – CK32K Clock Generator

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output duty cycle 48% 50% 52%
Output frequency 23 32.7 38 kHz

4.13 Thermal Characteristics

THERMAL METRIC(1) TUSB1211 UNIT
ZRQ (BGA MICROSTAR JUNIOR)
36 PINS
RθJA Junction-to-ambient thermal resistance(2) 69.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(3)(4) 41 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance(4)(5) N/A °C/W
RθJB Junction-to-board  thermal resistance or junction-to-pin thermal resistance(6) 42 °C/W
ΨJT Junction-to-top of package (not a true thermal resistance)(7) 0.9 °C/W
ΨJB Junction-to-board (not a true thermal resistance)(8) 71 °C/W
(1) For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal Metrics (SPRA953).
(2) Measurement method: EIA/JESD 51-1
(3) Top is surface of the package facing away from the PCB.
(4) No current JEDEC specification (see the application report, Semiconductor and IC Package Thermal Metrics (SPRA953).
(5) Bottom surface is the surface of the package facing towards the PCB.
(6) Measurement method: EIA/ JESD 51-8
(7) Measurement method: EIA/JESD 51-2
(8) Measurement method: EIA/JESD 51-6

4.14 REG3V3 Internal LDO Regulator Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VINREG3V3 Input voltage VBAT VOUT(typ) + 0.15 3.6 4.8 V
VVDD33 Output voltage
ACTIVE mode		 On mode – REG3V3_VSEL<2:0> = ‘000 2.4 2.5 2.6 V
On mode – REG3V3_VSEL<2:0> = ‘001 2.65 2.75 2.85
On mode – REG3V3_VSEL<2:0> = ‘010 2.9 3. 3.1
On mode – REG3V3_VSEL<2:0> = ‘011 (default) 3 3.1 3.2
On mode – REG3V3_VSEL<2:0> = ‘100 3.1 3.2 3.3
On mode – REG3V3_VSEL<2:0> = ‘101 3.2 3.3 3.4
On mode – REG3V3_VSEL<2:0> = ‘110 3.3 3.4 3.5
On mode – REG3V3_VSEL<2:0> = ‘111 3.4 3.5 3.6
VVDD33_DB Output voltage hardware charger detection
(dead battery) mode		 VBAT_DB < VBAT < 3.1 V VBAT – 0.05 VBAT VBAT + 0.05 V
VBAT > 3.1 V 3 3.1 3.2
IREG3V3 Rated output current VBAT: ACTIVE mode,
Hardware charger detection (dead battery) mode 		15 mA
IREG3V3_SUSP Rated output current:
IREG3V3_SUSP		 Suspend mode/reset mode 1 mA

4.15 REG1V8 Internal LDO Regulator Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VINREG1V8 Input voltage On mode : VINREG1V8 = VBAT 2.4 3.6 4.8 V
VREG1V8 Output voltage 1.75 1.87 1.98 V
IREG1V8 Rated output current On mode 30 mA

4.16 REG1V5 Internal LDO Regulator Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VINREG1V8 Input voltage On mode : VINREG1V8 = VBAT 2.4 3.6 4.8 V
VREG1V8 Output voltage 1.45 1.56 1.65 V
IREG1V8 Rated output current On mode 50 mA

4.17 Timers and Debounce

over operating free-air temperature range (unless otherwise noted)
PARAMETER NB CK32K CYCLES TEST CONDITIONS MIN TYP MAX UNIT
TDEL_CS_SUPPLYOK Chip-select-to-Supplies ok delay N/A 4.19 ms
TDEL_RST_DIR Resetb to PHY PLL locked and DIR falling-edge delay N/A 0.42 ms
TVBAT_DET VBAT detection delay N/A 10.0 µs
TBGAP Bandgap power-on delay N/A 2.0 ms
TPWONREG1V5 REG1V5 power-on delay N/A 100.0 µs
TPWONREG1V8 REG1V8 power-on delay N/A 100.0 µs
TPWONVREG3V3 REG3V3 power-on delay N/A 1.0 ms
TPWONCK32K 32KHz RC-OSC power-on delay N/A 125.0 µs
TDELRSTPWR Power control reset delay 2 52.6 61.0 87.0 µs
TDELMNTRVIOEN Monitor enable delay 3 78.9 91.6 130.4 µs
TMNTR Supply monitoring debounce 6 157.9 183.1 260.9 µs
TDELREG3V3EN REG3V3 LDO enable delay 3 78.9 91.6 130.4 µs
TDELRESET_N RESET_N internal delay 4 105.3 122.1 173.9 µs
TPLL PLL Lock time N/A 300.0 µs
TERROR_DELAY PWR FSM ERROR state delay Min 4100 107.9 125.1 356.3 ms
Max 8196

4.18 OTG VBUS Electrical

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBUS COMPARATORS
VA_VBUS_VLD A-device VBUS valid RVBUS = 0 Ω and R1KSERIES = 0 4.4 4.5 4.625 V
RVBUS = 1000 Ω ±10% and
R1KSERIES = 1		 4.4 4.5 4.625
RVBUS = 1200 Ω ±10% and
R1KSERIES = 1		 4.4 4.5 4.625
RVBUS = 1800 Ω ±10% and
R1KSERIES = 1		 4.4 4.5 4.675
VSESS_VLD A-device session valid 0.8 1.4 2.0 V
VB_SESS_VLD B-device session valid 2.1 2.4 2.7 V
VB_SESS_END B-device session end 0.2 0.5 0.8 V
VBUS LINE
RVBUS_IDLE_A A-device VBUS input impedance to ground SRP (VBUS pulsing) capable A-device not driving VBUS,
For VBUS < VSESS_VLD, (When bit RABUSIN_EN=1 RVBUS_IDLE_A / RVUS_IDLE_A_HI_RANGE impedance controlled automatically by hardware)		 40 100 kΩ
RVUS_IDLE_A_HI_RANGE A-device VBUS input impedance to ground (for VBUS hi-range) SRP (VBUS pulsing) capable A-device not driving VBUS
For VBUS > VSESS_VLD
(When bit RABUSIN_EN=1 RVBUS_IDLE_A / RVUS_IDLE_A_HI_RANGE impedance controlled automatically by hardware) 		70 100 kΩ
RVBUS_IDLE_B B-device VBUS input impedance to ground When bit RABUSIN_EN = 0
For VBUS in range [0 V : 20 V]
(Not valid for negative values of VBUS)		 150 220 400 kΩ
RB_SRP_DWN B-device VBUS SRP pulldown 5 10 20 kΩ
RB_SRP_UP B-device VBUS SRP pullup 0.85 1.3 1.75 kΩ
tRISE_SRP_UP_MAX B-device VBUS SRP rise time maximum for OTG-A communication 0 to 2.1 V
with < 13 μF load, 		RVBUS = 0 Ω and
R1KSERIES = 0		 31.4 ms
RVBUS = 1000 Ω ±10% and
R1KSERIES = 1 		57.8
RVBUS = 1200 Ω ±10% and
R1KSERIES = 1 		64
RVBUS = 1800 Ω ±10% and
R1KSERIES = 1 		85.4
tRISE_SRP_UP_MIN B-device VBUS SRP rise time minimum for standard host connection 0.8 to 2.0 V
with > 97 μF load,		 RVBUS = 0 Ω and
R1KSERIES = 0		 46.2 ms
RVBUS = 1000 Ω ±10% and
R1KSERIES = 1		 96
RVBUS = 1200 Ω ±10% and
R1KSERIES = 1		 100
RVBUS = 1800 Ω ±10% and
R1KSERIES = 1		 100
VBUS line maximum voltage –2 20 V

4.19 LS/FS Single-Ended Receivers

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
USB SINGLE-ENDED RECEIVERS
SKWVP_VM Skew between VP and VM Driver outputs unloaded –2 0 2 ns
VSE_HYS Single-ended hysteresis 50 mV
VIH High (driven) 2 V
VIL Low 0.8 V

4.20 LS/FS Differential Receiver

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDI Differential Input Sensitivity Ref. USB2.0 200 mV
VCM Differential Common Mode Range Ref. USB2.0 0.8 2.5 V

4.21 LS Transmitter

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low Ref. USB2.0 0 300 mV
VOH High (driven) Ref. USB2.0 2.8 3.6 V
VCRS Output signal crossover voltage Ref. USB2.0 1.3 2 V
TFR Rise time Ref. USB2.0,
covered by eye diagram		 75 300 ns
TFF Fall time Ref. USB2.0,
covered by eye diagram		 75 300 ns
TFRFM Differential rise and fall time matching 80% 125%
TFDRATE Low-speed data rate 1.4775 1.5225 Mb/s
Total source jitter
(including frequency tolerance):		 Ref. USB2.0, covered by eye diagram
TDJ1 To next transition –25 25 ns
TDJ2 For paired transitions –10 10
TFEOPT Source SE0 interval of EOP Ref. USB2.0,
covered by eye diagram		 1.25 1.5 µs
Downstream eye diagram Ref. USB2.0,
covered by eye diagram
VCM Differential common mode range Ref. USB2.0 0.8 2.5 V

4.22 FS Transmitter

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low Ref. USB2.0 0 300 mV
VOH High (driven) Ref. USB2.0 2.8 3.6 V
VCRS Output signal crossover voltage Ref. USB2.0 1.3 2 V
TFR Rise time Ref. USB2.0,
covered by eye diagram		 4 20 ns
TFF Fall time Ref. USB2.0 4 20 ns
TFRFM Differential rise and fall time matching Ref. USB2.0,
covered by eye diagram		 90% 111.11%
ZDRV Driver output resistance Ref. USB2.0 28 44 Ω
TFDRATE Full-speed data rate Ref. USB2.0,
covered by eye diagram		 11.97 12.03 Mb/s
Total source jitter
(including frequency tolerance):		 Ref. USB2.0,
covered by eye diagram
TDJ1 To next transition –2 2 ns
TDJ2 For paired transitions –1 1
TFEOPT Source SE0 interval of EOP Ref. USB2.0,
covered by eye diagram		 160 175 ns
Downstream eye diagram Ref. USB2.0,
covered by eye diagram
Upstream eye diagram

4.23 HS Transmitter

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VHSOI High-speed idle level Ref. USB2.0 –10 10 mV
VHSOH High-speed data signaling high Ref. USB2.0 360 440 mV
VHSOL High-speed data signaling low Ref. USB2.0 –10 10 mV
VCHIRPJ Chirp J level (differential voltage) Ref. USB2.0 700 1100 mV
VCHIRPK Chirp K level (differential voltage) Ref. USB2.0 –825 –500 mV
THSR Rise time (10% to 90%) Ref. USB2.0, covered by eye diagram 500 ps
Fall time (10% to 90%) 500
ZHSDRV Driver output resistance
(which also serves as high-speed termination)		 Ref. USB2.0 40.5 49.5 Ω
THSDRAT High-speed data range Ref. USB2.0, covered by eye diagram 479.76 480.24 Mb/s
Data source jitter Ref. USB2.0, covered by eye diagram
Downstream eye diagram Ref. USB2.0, covered by eye diagram
Upstream eye diagram Ref. USB2.0, covered by eye diagram

4.24 Pullup and Pulldown Resistors

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PULLUP RESISTORS
RPUI Bus pullup resistor on upstream port (idle bus) Bus idle 0.9 1.1 1.575 kΩ
RPUA Bus pullup resistor on upstream port (receiving) Bus driven, outputs of the driver unloaded 1.425 2.2 3.09
VIHZ High (floating) Pullups and pulldowns on both DP and DM lines 2.7 3.6 V
VPH_DP_UP DP pullup voltage Outputs of the driver unloaded 3 3.3 3.6 V
PULLDOWN RESISTORS
RPH_DP_DWN DP/DM pulldown Outputs of the driver unloaded 14.25 18 24.8 kΩ
RPH_DM_DWN
VIHZ High (floating) Pullups and pulldowns on both DP and DM lines 2.7 3.6 V
DP/-DATA LINE
VOTG_DATA_LKG On-the-go device leakage 0.342 V
ZINP Input impedance exclusive of pullup and pulldown  Outputs of the driver unloaded,
Measured at VDP or VDM = 0.8 V, and 2.0 V		 800 kΩ
CHARGER DETECTION PULLUP RESISTOR
RDP_WK_PU DP weak pullup resistor Measured at VBAT > VBAT_CERT 105 150 195 kΩ

4.25 Autoresume Watchdog Timer

over operating free-air temperature range (unless otherwise noted)
PARAMETER NB CK32K cycles TEST CONDITIONS MIN TYP MAX UNIT
TAUTORESUME Autoresume time-out 918 20.0 28.0 46.7 ms

4.26 UART Transceiver

over operating free-air temperature range (unless otherwise noted)
PARAMETER COMMENTS MIN TYP MAX UNIT
UART TRANSMITTER AT DM PIN
fUART_DFLT UART signaling rate 9600 bps
VOH_UART UART interface output high ISOURCE = 4 mA VVDD33 – 0.4 VVDD33 – 0.1 3.6 V
VOL_UART UART interface output low ISINK = –4 mA 0 0.1 0.4 V
UART RECEIVER AT DP PIN
VIH_UART UART interface input high DP_PULLDOWN asserted 2 V
VIL_UART UART interface input low DP_PULLDOWN asserted 0.8 V

4.27 OTG ID Electrical

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ID COMPARATORS — ID EXTERNAL RESISTORS SPECIFICATIONS
RID_FLOAT ID pulldown, when ID pin is floating Input spec for external ID resistor 220 kΩ
RID_A ACA ID pulldown, TUSB1211 is A-Device Input spec for external ID resistor 119 132 kΩ
RID_B ACA ID pulldown, TUSB1211 is B-Device, but can’t connect Input spec for external ID resistor 65 72 kΩ
RID_C ACA ID pulldown, TUSB1211 is B-Device, can connect Input spec for external ID resistor 35 39 kΩ
RIDGND ID pulldown when ID pin is grounded Input spec for external ID resistor 1 kΩ
ID DETECTION CIRCUITRY
RID_UP ID pullup resistor ID_PULLUP = ‘1, ID_WKPU = ‘0,
Measured for V(ID) = [0.9,2.7]V		 40 50 60 kΩ
RID_UP_WK ID weak pullup resistor ID_PULLUP = ‘1, ID_WKPU = ‘1,
Measured for V(ID) = [0.9,2.7]V		 300 400 500 kΩ
ID_R_ID_A_TO_FLOAT ID R_ID_A_TO_FLOAT comparator threshold Internal ID comparator threshold 132 182 220 kΩ
ID_R_ID_B_TO_A ID R_ID_B_TO_A comparator threshold Internal ID comparator threshold 72 103 119 kΩ
ID_R_ID_C_TO_B ID R_ID_C_TO_B comparator threshold Internal ID comparator threshold 39 55 65 kΩ
ID_R_ID_GND_TO_C ID ground-to-RID_C detection comparator threshold Internal ID comparator threshold ID_PULLUP = ‘1, ID_WKPU = ‘1 20 27 30 kΩ
VIDGND-to-RID_C ID ground-to-RID_C voltage detection threshold ID_PULLUP = ‘1, ID_WKPU = ‘1,
Valid for VBAT > VBAT_CERT max		 0.9 1.05 2.0 V
VID_MAX ID line maximum rated voltage 5.25 V
tID_DEB ID detection debounce time Min 48 cycles of CK32K clock
Max 64 cycles of CK32K clock		 1.3 1.5 2.8 ms
tID_MASK ID detection mask ID detection is masked for tID_MASK after IDPULLUP=1 or IDPULLUP_WK_EN=1 bits are enabled.
Min 1120 cycles of CK32K clock
Max 1152 cycles of CK32K clock During mask time TUSB1211 will indicate ID is grounded (ULPI RX CMD Bit6 = ID = 0).		 29.5 35.2 50.0 ms

4.28 Electrical Specs – Charger Detection Currents

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISUSP
(USB BC Ver1.1 spec)		 VBUS maximum current in dead battery. Maximum current the device is allowed to draw from VBUS in dead battery condition if VDP_SRC is not asserted Averaged over 1 s 1 mA
IVBAT_DET VBAT maximum current during battery charger detection 450 550 µA
IDP_SRC Data contact detect current source 7 13 µA
IDM_SINK DM sink current 50 150 µA
IDEV_HCHG_CHRP Portable device current from charging downstream port during chirp Refer to USB Battery Charging spec V1.1 Ch6.3.2 and values of VHSCM, and VCHIRPK 710 mA
IVDP_SRC_ILIM DP voltage source current limitation VDP = 0 V 800 µA

4.29 Electrical Specs – Resistance

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RDP_DWN DP pulldown resistance 14.25 24.8 kΩ
RDM_DWN DP pulldown resistance 14.25 24.8 kΩ
RDCHG_DAT Dedicated charging port resistance across DP/DM (input spec to TUSB1211) 200 Ω
RDCHRGR_PWR Dedicated charging port resistance from DP/DM to VBUS/GND (input spec to TUSB1211) 2 MΩ

4.30 Electrical Specs – Capacitance

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CDCHG_PWR Dedicated charging port capacitance from DP or DP to VBUS or GND (input spec to TUSB1211) 1 nF

4.31 Charger Detection Debounce and Wait Timing

over operating free-air temperature range (unless otherwise noted)
PARAMETER NB CK32K CYCLES TEST CONDITIONS BC1.1
SPEC 		MIN TYP MAX UNIT
DEBVBUS_TIME VBUS debounce time 459 > 10 12.1 14.0 20.0 ms
TIDP_SRC_ON DP Current source on-time 8 > 200 210.5 244.1 347.8 µA
TVDP_SRC_ON DP Voltage source on-time 1792 > 40 47.2 54.7 77.9 ms
TVDP_SRC_HICRNT DP Voltage source off to high current on charger delay 1792 > 40 47.2 54.7 77.9 ms
TDCD_TIMEOUT Data contact detect timeout 89400 > 2 2.4 2.7 3.9 s
TSVLD_CON_WKB Session valid to connect for peripheral with dead or weak battery 53084160 Used to generate SVLDCONWKB_CNTR in FSM < 45 27.0 23.3 38.5 min
TVDPSRC_CON DP voltage source off to connect delay N/A Input spec > 40 N/A N/A N/A ms
TVDPSRC_DEB VDP_SRC comparator debounce time 760 Used to generate CHGD_VDM_DEB in FSM N/A 20.0 23.2 33.0 ms
TCHGD_SERX_DEB Charger detect SERX debounce time 1520 Used to generate CHGD_SERX_DP_DEB and CHGD_SERX_DM_DEB in FSM N/A 40.0 46.4 66.1 ms
TACA_SETUP ACA setup time 2300 N/A 60.5 70.2 100.0 ms
TID_RARBRC_DEB ACA ID RA, RB, RC comparators debounce 1520 Used to generate ID_RARBRC_DEB in FSM N/A 40.0 46.4 66.1 ms

4.32 ULPI Interface

4.32.1 ULPI Interface Timing

Table 4-1 ULPI Interface Timing

PARAMETER SYMBOL MIN MAX UNIT
OUTPUT CLOCK
Setup time (control in, 8-bit data in) TSC, TSD 6 ns
Hold time (control in, 8-bit data in) TSC, THD 0 ns
Output Delay (control out, 8-bit data out) TDC, TDD 6.5 ns
INPUT CLOCK
Setup time (control in, 8-bit data in) TSC, TSD 3 ns
Hold time (control in, 8-bit data in) TSC, THD 1.5 ns
Output Delay (control out, 8-bit data out) TDC, TDD 6 ns

4.33 Power-On Timing Diagrams

4.33.1 Standard Power-up Timing

This scenario corresponds to standard power-up of TUSB1211 device in presence of valid VBAT, VIO, and chip selected (CS = 1 and CS_N = 0).

A timing diagram for standard power up is shown in Figure 4-1. In this plot USB ULPI clock is configured in output mode. A suggested application diagram for this configuration is shown in Section 6.

NOTE

The ULPI clock can also be configured in input mode, see Figure 4-1 for details.
TUSB1211 stdrpwruptim_llse44.gifFigure 4-1 Power-Up Timing: (ULPI Clock Output Mode), Normal Battery

4.33.2 Hardware Charger Detection Power-Up Timing

This scenario corresponds to “dead battery” scenario in USB Battery Charging Specification V1.1.

Here VBUS is plugged while chip is not enabled (CS = 0 or CS_N = 1 or both), with VBAT > VBAT_DET. This causes the device to power up to and initiate Charger Detection through hardware. See Section 5.3.12 for details.

TUSB1211 hardwarechargdet_llse44.gifFigure 4-2 Power-Up Timing (ULPI Clock Output Mode), "Dead" Battery

4.34 Clock System

4.34.1 USB PLL Reference Clock

The USB PLL block generates the clocks used to synchronize:

  • the ULPI interface (60 MHz clock)
  • the USB interface (depending on the USB data rate, 480 Mbps, 12 Mbps or 1.5 Mbps)

TUSB1211 requires an external reference clock which is used as an input to the 480MHz USB PLL block. Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at CLOCK pin.

By default CLOCK pin is configured as an input.

Two clock configurations are possible:

4.34.1.1 ULPI Input Clock Configuration

In this mode REFCLK must be externally tied to GND.

CLOCK remains configured as an input.

When the ULPI interface is used in “input clock configuration”, that is, the 60 MHz ULPI clock is provided to TUSB1211 on CLOCK pin, then this is used as the reference clock for the 480 MHz USB PLL block.

4.34.1.2 ULPI Output Clock Configuration

In this mode a reference clock must be externally provided on REFCLK pin.

When an input clock is detected on REFCLK pin then CLOCK will automatically change to an output, that is, 60 MHz ULPI clock is output by TUSB1211 on CLOCK pin.

Two reference clock input frequencies are supported. REFCLK input frequency is communicated to TUSB1211 through a configuration pin, CFG, see FREFCLK in Section 4.11 for frequency correspondence.

TUSB1211 supports square-wave reference clock input only.

4.35 Clock System

4.35.1 Internal Clock Generator (32 kHz)

An internal clock generator running at 32 kHz has been implemented to provide a low speed low power clock to the system. This is referred to as CK32K elsewhere in this specification.

4.36 Power Management

This chapter describes the electrical characteristics of the voltage regulators and timing characteristics of the supplies digitally controlled within the TUSB1211 device.

4.36.1 Power Provider

Table 4-2 Summary of Internal Power Providers(1)

SUPPLY NAME PIN NAME TYPE TYPICAL VOLTAGE (V)
REG1V5 REG1V5 LDO 1.5
REG1V8 — LDO 1.8
REG3V3 REG3V3 LDO 3.1
(1) REG3V3 may be supplied externally, or by shorting the REG3V3 pin to VBAT pin provided VBAT min is in range [3.2 V : 3.6 V]. Note that the REG3V3 LDO will always power-on when the chip is enabled, irrespective of whether VDD33 is supplied externally or not.

4.37 Power Provider

Table 4-3 Summary of the Power Provider

LDO NAME PIN NAME USAGE TYPE TYPICAL VOLTAGE (V) MAXIMUM CURRENT
REG1V5 REG1V5 Internal LDO 1.5 50 mA
REG1V8 — Internal (capless) LDO 1.8 30 mA
REG3V3 REG3V3 Internal LDO 3.1 15 mA

4.37.1 REG3V3 Regulator

The REG3V3 internal LDO regulator powers the USB PHY, Charger detection, and OTG functions of the USB subchip inside TUSB1211.

It takes its power from the VBAT pin. It is connected to an external filtering capacitor at the REG3V3 pin (E3).

The USB standard requires data lines to be biased with pullups powered from a >3.0 V supply. Hence TUSB1211 cannot be guaranteed USB2.0 compliant for VBAT voltage lower than VBAT_CERT. TUSB1211 will however keep operating below this voltage.

4.37.2 REG1V8 Regulator

The REG1V8 internal LDO regulator powers the USB PHY, and USB PLL.

It takes its power from the VBAT pin. This LDO is capless, that is, its output is not connected to any external pin.

Section 4.15 describes its characteristics.

4.37.3 REG1V5 Regulator

The REG1V5 internal LDO regulator powers the USB PHY and internal digital circuitry of TUSB1211. Section 4.16 describes the regulator characteristics.

It takes its power from the VBAT pin. It is connected to an external filtering capacitor at the REG1V5 pin (E6).

4.38 Power Control

TUSB1211 can be powered up in two different modes:

  • Standard power-up condition

    • For this, VBAT and VIO must be present and chip must be selected (CS=1 and CS_N=0). See Section 4.33.1. Standard Power-up Timing Power resources will be configured sequentially until the device reaches the power state.

    USBON . At this time internal power-on-reset signal PORZ will be released and USB PLL will start up. Once PLL is locked, the DIR output pin will be deasserted allowing TUSB1211 to be configured by the USB Link Controller through the ULPI interface.

    Note that by default TUSB1211 will be configured as a Host not providing VBUS as required by register map in ULPI specification Rev1.1.

    This is the case because OTG_CONTROL register bits DRVVBUS and DRVVBUSEXTERNAL bits are 0 by default, and DPPULLDOWN, DMPULLDOWN bits are 1 by default such that the 15 kΩ pulldown resistors at DP/DM pins are enabled by default.

    It is the responsibility of the link to enable external VBUS supply if required in Host mode, or to reconfigure the PHY if required in Device mode.

  • Hardware charger detection power-up

    • When the chip is not selected (CS=0 or CS_N=1), but VBUS is present and CHRG_EN_N pin is at GND, and VBAT > VBAT_MNTR then TUSB1211 will power-up in Hardware Charger Detection Mode.

    Power resources will be configured sequentially until the device reaches the power state USBON. However, because the chip is not selected, the internal power-on-reset signal PORZ will be not be released and USB PLL will not start up. Instead the device will enter the USB battery charger finite state machine (FSM) .