JAJSDO7A August   2017  – September 2017 TUSB214-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 EQ
      2. 7.3.2 DC BOOST
      3. 7.3.3 BC1.2 CDP Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Speed (LS) Mode
      2. 7.4.2 Full Speed (FS) Mode
      3. 7.4.3 High Speed (HS) Mode
      4. 7.4.4 Shutdown Mode
      5. 7.4.5 I2C Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram
          1. 8.2.2.1.1 For a Host Side Application
          2. 8.2.2.1.2 For a Device Side Application
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RWB Package
12 Pin (X2QFN)
Top View
TUSB214-Q1 RWB_po_SLLSEX5.gif

Pin Functions

PIN I/O INTERNAL
PULLUP/PULLDOWN		 DESCRIPTION
NAME NO.
D1M 1 I/O N/A USB High Speed negative port..
D1P 2 I/O N/A USB High Speed positive port.
SDA(1) 3 I/O RSTN asserted: 500 kΩ PD I2C Mode:
Bidirectional I2C data pin [I2C address = 0x2C].
In non I2C mode:
Reserved for TI test purpose.
SCL(1)/CD 4 I/O RSTN asserted: 500 kΩ PD In I2C mode:
I2C clock pin [I2C address = 0x2C].
Non I2C mode:
After reset: Output CD. Flag indicating that a USB device is attached (connection detected). Asserted from an unconnected state upon detection of DP or DM pull-up resistor. De-asserted upon detection of disconnect.
RSTN 5 I 500 kΩ PU Device disable/enable.
Low – Device is at reset and in shutdown, and
High – Normal operation.
Recommend 0.1-µF external capacitor to GND to ensure clean power on reset if not driven.
If the pin is driven, it must be held low until the supply voltage for the device reaches within specifications.
EQ 6 I N/A USB High Speed AC boost select via external pull down resistor.
Sampled upon de-assertion of RSTN. Does not recognize real time adjustments.
Auto selects max AC Boost when left floating.
D2P 7 I/O N/A USB High Speed positive port.
D2M 8 I/O N/A USB High Speed negative port.
DC_BOOST(2)/ENA_HS 9 I/O In I2C mode:
Reserved for TI test purpose.
In non-I2C mode:
At reset: 3-level input signal DC_BOOST. USB High Speed DC signal boost selection.
H (pin is pulled high) – 80 mV
M (pin is left floating) – 60 mV
L (pin is pulled low) – 40 mV
After reset: Output signal ENA_HS. Flag indicating that channel is in High Speed mode. Asserted upon:
1. Detection of USB-IF High Speed test fixture from an unconnected state followed by transmission of USB TEST_PACKET pattern.
2. Squelch detection following USB reset with a successful HS handshake [HS handshake is declared to be successful after single chirp J chirp K pair where each chirp is within 18 μs – 128 μs].
GND 10 P N/A Ground
VREG 11 O N/A 1.8-V LDO output. Only enabled when operating in High Speed mode. Requires 0.1-µF external capacitor to GND to stabilize the core.
VCC 12 P N/A Supply power
(1) Pull-up resistors for SDA and SCL pins in I2C mode should be 4.7 kΩ (5%). If both SDA and SCL are pulled up at reset the device enters into I2C mode.
(2) Pull-down and pull-up (to 3.3 V) resistors for DC_BOOST pins must be between 22 kΩ to 47 kΩ in non I2C mode.