JAJSG68A September   2018  – December 2018 TUSB217-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High speed boost
      2. 7.3.2 RX Sensitivity
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Speed (LS) mode
      2. 7.4.2 Full Speed (FS) mode
      3. 7.4.3 High Speed (HS) mode
      4. 7.4.4 High Speed downstream port electrical compliance test mode
      5. 7.4.5 Shutdown mode
      6. 7.4.6 I2C mode
    5. 7.5 TUSB217 Registers
      1. 7.5.1 EDGE_BOOST Register (Offset = 0x1) [reset = X]
        1. Table 4. EDGE_BOOST Register Field Descriptions
      2. 7.5.2 CONFIGURATION Register (Offset = 0x3) [reset = X]
        1. Table 5. CONFIGURATION Register Field Descriptions
      3. 7.5.3 DC_BOOST Register (Offset = 0xE) [reset = X]
        1. Table 6. DC_BOOST Register Field Descriptions
      4. 7.5.4 RX_SEN Register (Offset = 0x25) [reset = X]
        1. Table 7. RX_SEN Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram
          1. 8.2.2.1.1 For a Host Side Application
          2. 8.2.2.1.2 For a Device Side Application
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGY|14
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGY Package
14 Pin (VQFN)
Top View
TUSB217-Q1 pinout-217Q1-rgy.gif

Pin Functions

PIN I/O INTERNAL
PULLUP/PULLDOWN		 DESCRIPTION
NAME NO. (RGY)
BOOST 1 I N/A USB High Speed boost select via external pull down resistor.
Both edge boost and DC boost are controlled by a single pin in non-I2C mode. In I2C mode edge boost and DC boost can be individually controlled.
Sampled upon power up. Does not recognize real time adjustments.
Auto selects BOOST LEVEL = 3 when left floating.
NC 2,3 I Leave unconnected
RESERVED 8 O Leave unconnected or connect a decoupling cap 0.1μF
RX_SEN(2)/ENA_HS 4 I/O N/A In I2C mode:
Reserved for TI test purpose.
In non-I2C mode:
At reset: 3-level input signal RX_SEN. USB High Speed RX Sensitivity Setting to Compensate ISI Jitter
H (pin is pulled high) – high RX sensitivity (high loss channel)
M (pin is left floating) – medium RX sensitivity (medium loss channel)
L (pin is pulled low) – low RX sensitivity (low loss channel)
After reset: Output signal ENA_HS. Flag indicating that channel is in High Speed mode. Asserted upon:
1. Detection of USB-IF High Speed test fixture from an unconnected state followed by transmission of USB TEST_PACKET pattern.
2. Squelch detection following USB reset with a successful HS handshake [HS handshake is declared to be successful after single chirp J chirp K pair where each chirp is within 18 μs – 128 μs].
D2P 5 I/O N/A USB High Speed positive port.
D2M 6 I/O N/A USB High Speed negative port.
GND 7 P N/A Ground
D1M 9 I/O N/A USB High Speed negative port..
D1P 10 I/O N/A USB High Speed positive port.
SDA(1) 11 I/O 500 kΩ PU
1.8 MΩ PD		 I2C Mode:
Bidirectional I2C data pin [7-bit I2C slave address = 0x2C].
In non I2C mode:
Reserved for TI test purpose.
VCC 12 P N/A Supply power
RSTN 14 I 500 kΩ PU
1.8 MΩ PD		 Device disable/enable.
Low – Device is at reset and in shutdown, and
High - Normal operation.
Recommend 0.1-µF external capacitor to GND to ensure clean power on reset if not driven. If the pin is driven, it must be held low until the supply voltage for the device reaches within specifications.
SCL(1)/CD 13 I/O When RSTN asserted there is a 500 kΩ PD In I2C mode:
I2C clock pin [I2C address = 0x2C].
Non I2C mode:
After reset: Output CD. Flag indicating that a USB device is attached (connection detected). Asserted from an unconnected state upon detection of DP or DM pull-up resistor. De-asserted upon detection of disconnect.
Thermal Pad TPAD N/A N/A Thermal Pad is electrically not connected to device ground. Connection to board ground is optional.
(1) Pull-up resistors for SDA and SCL pins in I2C mode should be RPull-up (depending on I2C bus voltage). If both SDA and SCL are pulled up at power-up the device enters into I2C mode.
(2) Pull-down and pull-up resistors for RX_SEN pin must follow RRXSEN1 and RRXSEN2 resistor recommendations in non I2C mode.