JAJSOK4D November   2021  – April 2024 TUSB2E11

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Version Comparison
    1. 4.1 Device Variants
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1  Repeater Mode
      2. 8.4.2  Power Down Mode
      3. 8.4.3  Disabled Mode
      4. 8.4.4  UART Mode
      5. 8.4.5  Auto-Resume ECR
      6. 8.4.6  L2 State Interrupt Modes
      7. 8.4.7  Attach Detect Interrupt Mode
      8. 8.4.8  GPIO Mode
      9. 8.4.9  USB 2.0 High-Speed HOST Disconnect Detection
      10. 8.4.10 Frame Based Low Power Mode
      11. 8.4.11 Battery Charging
    5. 8.5 Manufacturing Test Modes
      1. 8.5.1 USB DP Test Procedure
      2. 8.5.2 USB DM Test Procedure
    6. 8.6 I2C Target Interface
  10. Register Access Protocol (RAP)
  11. 10Register Map
    1. 10.1 TUSB2E11 Registers
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 Power Supply Recommendations
      1. 11.3.1 Power Up Reset
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Example Layout for Application with 1.8V I2C Variant
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

I2C Target Interface

I2C target interface enables access to internal registers by the system application processor. The primary function of the interface is to enable configuring various PHY parameters, controlling the GPIO pins, and enabling USB-BC functions. The TUSB2E11 repeater functions operate upon power up without requiring I2C configuration.

The TUSB2E11 has I2C 7-bit target address of 0x3E. 8-bit address of Write: 0x7C and Read: 0x7D.

I2C default target address can be changed at the factory through one time programming.

I2C drive strength can be changed through the I2C.

Table 8-6 Recommended I2C Drive Strength for I2C Bus Speed, Bus Pull Up and Bus Capacitance
I2C FM+ (1MHz Max) I2C drive strength (IOL) selection
I2C bus pullup RPU
C(bus)pF 1kΩ 2.2kΩ 4kΩ 7kΩ
10-50 ≅8mA ≅4mA N/A N/A
10-90 ≅8mA N/A N/A N/A
10-150 N/A N/A N/A N/A
10-200 N/A N/A N/A N/A
I2C FM (400kHz Max) I2C drive strength (IOL) selection
I2C bus pullup RPU
C(bus)pF 1kΩ 2.2kΩ 4kΩ 7kΩ
10-50 ≅8mA ≅4mA ≅2mA N/A
10-90 ≅8mA ≅4mA N/A N/A
10-150 ≅8mA ≅8mA N/A N/A
10-200 ≅8mA N/A N/A N/A
I2C STD (100kHz Max) I2C drive strength (IOL) selection
I2C bus pullup RPU
C(bus)pF 1kΩ 2.2kΩ 4kΩ 7kΩ
10-50 ≅8mA ≅4mA ≅2mA ≅1mA
10-90 ≅8mA ≅4mA ≅2mA ≅1mA
10-150 ≅8mA ≅4mA ≅2mA ≅2mA
10-200 ≅8mA ≅4mA ≅2mA ≅2mA
GUID-B546FCFA-BF6D-4476-A4F0-2E8E894921E1-low.png Figure 8-5 I2C Write with Data

Use the following procedure to write data to the TUSB2E11 I2C registers (refer to Figure 8-5):

  1. The host initiates a write operation by generating a start condition (S), followed by the TUSB2E11 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB2E11 acknowledges the address cycle.
  3. The host presents the register offset within the TUSB2E11 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB2E11 acknowledges the sub-address cycle.
  5. The host presents the first byte of data to be written to the I2C register.
  6. The TUSB2E11 acknowledges the byte transfer.
  7. The host may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB2E11.
  8. The host terminates the write operation by generating a stop condition (P).

GUID-8DE50435-51EE-4B11-BFBE-435C067DB6B5-low.png Figure 8-6 I2C Read Without Repeated Start

Use the following procedure to write data to the TUSB2E11 I2C registers without a repeated Start (refer Figure 8-6).

  1. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E11 7-bit address and a zero-value “W/R” bit to indicate a read cycle.
  2. The TUSB2E11 acknowledges the 7-bit address cycle.
  3. Following the acknowledge the host continues sending clock.
  4. The TUSB2E11 transmit the contents of the memory registers MSB-first starting at register 00h or last read register offset+1. If a write to the I2C register occurred prior to the read, then the TUSB2E11 shall start at the register offset specified in the write.
  5. The TUSB2E11 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after each byte transfer; the I2C host acknowledges reception of each data byte transfer.
  6. If an ACK is received, the TUSB2E11 transmits the next byte of data as long as host provides the clock. If a NAK is received, the TUSB2E11 stops providing data and waits for a stop condition (P).
  7. The host terminates the write operation by generating a stop condition (P).

GUID-0CD76484-C1C4-4B85-A8B7-D10D38D14717-low.png Figure 8-7 I2C Read with Repeated Start

Use the following procedure to write data to the TUSB2E11 I2C registers with a repeated Start (refer Figure 8-7).

  1. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E11 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB2E11 acknowledges the 7-bit address cycle.
  3. The host presents the register offset within the TUSB2E11 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB2E11 acknowledges the register offset cycle.
  5. The host presents a repeated start condition (Sr).
  6. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E11 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  7. The TUSB2E11 acknowledges the 7-bit address cycle.
  8. The TUSB2E11 transmit the contents of the memory registers MSB-first starting at the register offset.
  9. The TUSB2E11 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after each byte transfer; the I2C host acknowledges reception of each data byte transfer.
  10. If an ACK is received, the TUSB2E11 transmits the next byte of data as long as host provides the clock. If a NAK is received, the TUSB2E11 stops providing data and waits for a stop condition (P).
  11. The host terminates the read operation by generating a stop condition (P).

GUID-DCAD5E57-B72B-44E2-941D-2B26EFDCDBC6-low.png Figure 8-8 I2C Write Without Data

Use the following procedure to set a starting sub-address for I2C reads (refer to Figure 8-8).

  1. The host initiates a write operation by generating a start condition (S), followed by the TUSB2E11 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB2E11 acknowledges the address cycle.
  3. The host presents the register offset within the TUSB2E11 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB2E11 acknowledges the register offset cycle.
  5. The host terminates the write operation by generating a stop condition (P).

Note: After initial power-up, if no register offset is included for the read procedure (refer to Figure 8-6), then reads start at register offset 00h and continue byte by byte through the registers until the I2C host terminates the read operation. During a read operation, the TUSB2E11 auto-increments the I2C internal register address of the last byte transferred independent of whether or not an ACK was received from the I2C host.
GUID-409CA334-F138-4BA6-92F5-4AAF1D964D98-low.gif Figure 8-9 I2C Timing Diagram