JAJSOK4D November   2021  – April 2024 TUSB2E11

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Version Comparison
    1. 4.1 Device Variants
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1  Repeater Mode
      2. 8.4.2  Power Down Mode
      3. 8.4.3  Disabled Mode
      4. 8.4.4  UART Mode
      5. 8.4.5  Auto-Resume ECR
      6. 8.4.6  L2 State Interrupt Modes
      7. 8.4.7  Attach Detect Interrupt Mode
      8. 8.4.8  GPIO Mode
      9. 8.4.9  USB 2.0 High-Speed HOST Disconnect Detection
      10. 8.4.10 Frame Based Low Power Mode
      11. 8.4.11 Battery Charging
    5. 8.5 Manufacturing Test Modes
      1. 8.5.1 USB DP Test Procedure
      2. 8.5.2 USB DM Test Procedure
    6. 8.6 I2C Target Interface
  10. 9 Register Access Protocol (RAP)
  11. 10Register Map
    1. 10.1 TUSB2E11 Registers
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 Power Supply Recommendations
      1. 11.3.1 Power Up Reset
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Example Layout for Application with 1.8V I2C Variant
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PWC_1V8 Absolute worst case peak power consumption (VDD1V8 only) for power supply budgeting I2C interface active,  GPIOs in output mode, repeater in HS mode with USB transmitting, maximum RX EQ, max TX VOD and PE settings, maximum transition density. TA = −20°C to 85°C. 280 mW
PWC_3V3 Absolute worst case peak power consumption (VDD3V3 only) for power supply budgeting I2C interface active,  GPIOs in output mode, repeater in HS mode with USB transmitting, maximum RX EQ, max TX VOD and PE settings, maximum transition density. TA = –20°C to 85°C. 30 mW
PWCFS_3V3 Absolute worst case peak power consumption (VDD3V3 only) for power supply budgeting  I2C interface active,  GPIOs in output mode, repeater in FS mode with USB Asynchronous traffic. TA = –20°C to 85°C. 75 mW
PHS_IOC USB Audio ISOC High-speed  Maximum TX Vod/Maximum TX PE for both USB and eUSB2. Averaged over 8 ms and only 1 uFrame with data packet. Toff threshold = 1/32. Host Peripheral Mode. 35 mW
PPD Powered down  Device powered, RESETB=Low, TA=25°C, (DP/DN Voltage ≤ VDD3V3). 9 µW
PDisabled Disabled Device powered, I2C/GPIO interfaces functional but idle, repeater is disabled and put into the lowest power state and non-functional. TA=25°C, (DP/DN Voltage ≤ VDD3V3). 43 95 µW
PDetach USB unconnected  I2C/GPIO interfaces idle, repeater is connected to a eUSB2 PHY and waiting for a USB attach event. TA = 25°C, (DP/DN Voltage ≤ VDD3V3) 43 85 µW
PSuspend L2 Suspend (host mode) I2C/GPIO interfaces idle, USB link is in L2, repeater is monitoring for a resume/remote wake event. TA = 25°C, (DP/DN Voltage ≤ VDD3V3). In peripheral mode additional current is present due the DP pull up. 45 85 µW
PSleep L1 Sleep  I2C/GPIO interfaces idle, repeater is supporting a USB connection, USB link is in L1 (host exists L1 every 1 ms) and repeater is monitoring for a L1 exit event. TA = 25°C, (DP/DN Voltage ≤ VDD3V3)  2.3 5 mW
PLS_Active Low Speed Active  I2C/GPIO interfaces idle, repeater in LS mode, maximum transition density. TA = 85°C. 7.2 24 mW
PFS1_Active Full Speed Active (ASYNC Traffic) I2C/GPIO interfaces idle, repeater in FS mode, maximum transition density. TA = 85°C. 45 80 mW
PFS2_Active Full Speed Active (ISO Traffic) I2C/GPIO interfaces idle, repeater in FS mode, maximum transition density. TA = 85°C. 9 24 mW
PHS_Idle_Host High Speed Idle (Host mode)  L0.Idle. TA = 85°C. (Typical at 25°C).  26 70 mW
PHS_Idle_Peripheral High Speed Idle (Peripheral mode) L0.Idle. TA = 85°C. (Typical at 25°C). 108 200 mW
DIGITAL INPUTS
VIH High level input voltage GPIO0, GPIO1, GPIO2 (1.2 V Variant) 0.702 V
VIH High level input voltage GPIO0, GPIO1, GPIO2 (1.8 V Variant) 1.053 V
VIL Low-level input voltage GPIO0, GPIO1, GPIO2 (1.2 V Variant) 0.462 V
VIL Low-level input voltage GPIO0, GPIO1, GPIO2 (1.8 V Variant) 0.693 V
VIL Low-level input voltage RESETB 0.35 V
VIH High level input voltage RESETB 0.75 V
IIH High level input current VIH = 1.98 V, VDD3V3=3.0 V or 0 V, VDD1V8=1.62 V or 0 V
RESETB, GPIO0, GPIO1		 0.5 µA
IIL Low level input current VIL = 0 V, VDD3V3=3.0 V or 0 V, VDD1V8=1.62 V or 0 V
RESETB, GPIO0, GPIO1		 0.5 µA
DIGITAL OUTPUTS
VOH High level output voltage  GPIO0, GPIO1, GPIO2, push-pull I/O mode (IOH = 20 µA and maximum 3 pF Cload) (1.2 V Variant) 0.81 V
VOH High level output voltage  GPIO0, GPIO1, GPIO2, push-pull I/O mode (IOH = 20 µA and maximum 3 pF Cload)(1.8 V Variant) 1.21 V
VOL Low level output voltage GPIO0, GPIO1, GPIO2, push-pull I/O mode (IOL = 1 mA) (1.2 V Variant) 0.25 V
VOL Low level output voltage GPIO0, GPIO1, GPIO2, push-pull I/O mode (IOL = 1 mA) (1.8 V Variant) 0.35 V
IOL_PP Low level output current in push-pull mode
GPIO0, GPIO1, GPIO2 (1.2 V Variant), VOL=0.4 V		 2.5 4 5.6 mA
IOL_PP Low level output current in push-pull mode GPIO0, GPIO1, GPIO2 (1.8 V Variant), VOL=0.4 V 4 6 8 mA
IOH_PP High level output current in push-pull mode GPIO0, GPIO1, GPIO2, push-pull I/O mode, VOH=0.9 V (1.2 V Variant)  22 µA
IOH_PP High level output current in push-pull mode GPIO0, GPIO1, GPIO2, push-pull I/O mode, VOH=0.9 V  (1.8 V Variant) 50 µA
I2C (SDA, SCL)
VIL Low level input voltage, 1.2 V variant SDA, SCL, V_I2C_Pullup = 1.08 V 0.387 V
VIL Low level input voltage, 1.8 V variant SDA, SCL, V_I2C_Pullup = 1.96 V 0.588 V
VIH High level input voltage, 1.2 V variant SDA, SCL, V_I2C_Pullup = 1.08 V 0.833 V
VIH High level input voltage, 1.8 V variant SDA, SCL, V_I2C_Pullup = 1.96 V 1.372 V
VHYS Input hysteresis, 1.2 V variant V_I2C_Pullup = 1.08 V 0.020 V
VHYS Input hysteresis, 1.8 V variant V_I2C_Pullup = 1.96 V 0.098 V
IIH High level input leakage current VIH = 1.98 V 0.5 µA
IIL Low level input leakage current VIL = 0 V 0.5 µA
VOL Low level output voltage (1 kΩ pull up), 1.2 V variant IOL = 2.5 mA, V_I2C_Pullup = 1.08 V 0.2 V
VOL Low level output voltage (1 kΩ pull up), 1.8V variant IOL = 2.5 mA, V_I2C_Pullup = 1.96 V 0.3 V
IOL Open drain drive strength, 1.2 V Variant VOL = 0.4 V 1.6 2.4 3.0 mA
IOL Open drain drive strength, 1.8 V Variant VOL = 0.4 V 8 10 12.6 mA
UART I/O
VOLI Internal output low Internal UART output (eDP/eDN) 1.2 V signaling 0.1 V
VOHI Internal output high Internal UART output (eDP/eDN) 1.2 V signaling 0.918 1.32 V
VILI Internal input low Internal UART input (eDP/eDN) 1.2 V signaling –0.1 0.399 V
VIHI Internal input high Internal UART input (eDP/eDN) 1.2 V signaling 0.819 1.386 V
VOLE External output low External UART output (DP/DN) 3.3 V signaling 0 0.3 V
VOHE External output high External UART output (DP/DN) 3.3 V signaling 2.8 3.6 V
VILE External input low External UART input (DP/DN) 3.3 V signaling 0.8 V
VIHE External input high External UART input (DP/DN) 3.3 V signaling 2 V
USB (DP, DN)
Zinp_Dx Impedance to GND, no pull up or pull down Vin=3.6 V, VDD3V3=3.0 V, Input Characteristics(1) 390 kΩ
CIO_Dx Capacitance to GND Measured with VNA at 240 MHz, Driver Hi-Z 10 pF
RPUI Bus pull-up resistor on upstream facing port (idle) High-speed Device Speed Identification(1) 0.92 1.1 1.475 kΩ
RPUR Bus pull-up resistor on upstream facing port (receiving) High-speed Device Speed Identification(1) 1.525 2.2 2.99 kΩ
RPD Bus pull-down resistor on downstream facing port High-speed Device Speed Identification(1) 14.35 19 24.6 kΩ
VHSTERM Termination voltage in high speed The output voltage in the high-speed idle state, High-speed Input Characteristics(1) –10 10 mV
USB TERMINATION
ZHSTERM_P Driver Output Resistance (which also serves as high speed termination) (VOH= 0 to 600 mV) Full-speed (12 Mb/s) Driver Characteristics(1), Default, U_HS_TERM_Px setting 01 40.6 45 49.4 Ω
ZHSTERM_N Driver Output Resistance (which also serves as high speed termination) (VOH= 0 to 600 mV) Full-speed (12 Mb/s) Driver Characteristics(1), Default, U_HS_TERM_Px setting 01 40.6 45 49.4 Ω
USB INPUT LEVELS LS/FS
VIH High (driven) Receiver Characteristics(1) (measured at the connector) 2 V
VIHZ High (floating) Receiver Characteristics(1)  (HOST downstream port pull-down resistor enabled and external device pull up 1.5 kΩ ± 5% to 3.0-3.6 V) 2.7 3.6 V
VIL Low Receiver Characteristics(1) 0.8 V
VDI Differential Input Sensitivity (hysteresis is off) |(D+)-(D-)|; Differential Input Sensitivity Range for Low-/full-speed(1); (measured at connector) VCM=0.8 V to 2.0 V 0.2 V
USB OUTPUT LEVELS LS/FS
VOL Low USB Driver Characteristics(1), (measured at connector with RL of 1.425 kΩ to 3.6 V. ) 0 0.3 V
VOH High (Driven) USB Driver Characteristics(1), (measured at the connector with RL of 14.25 kΩ to GND. ) 2.8 3.6 V
ZFSTERM Driver Series Output Resistance USB Driver Characteristics(1), measured it during VOL or VOH 28 44 Ω
VCRS2 Output Signal Crossover Voltage Measured as in Data Signal Rise and Fall Time(1), excluding the first transition from the Idle state. With external 1.5 kΩ pull up on DP to 3.0 V 1.3 2 V
VCRS Output Signal Crossover Voltage Measured as in Data Signal Rise and Fall Time(1), excluding the first transition from the Idle state 1.3 2 V
USB INPUT LEVELS HS
VHSSQ High-speed squelch/no-squelch detection threshold  Full-/High-speed Signaling Level(1), specification refers to peak differential signal amplitude), measured at 240 MHz with increasing amplitude, U_SQUELCH_THRESHOLD_Px setting 011, VCM= -50 mV to 500 mV 111 128 161 mV
VHSSQ High-speed squelch/no-squelch detection threshold  Full-/High-speed Signaling Levels(1), (specification refers to peak differential signal amplitude), measured at 240 MHz with increasing amplitude,
U_SQUELCH_THRESHOLD_Px setting 100, VCM= -50 mV to 500 mV		 104 125 150 mV
VHSDSC High-speed disconnect detection threshold  Full-/High-speed Signaling Levels(1), (specification refers to differential signal amplitude). (HW Default),
U_DISCONNECT_THRESHOLD_Px setting 0000, VCM=200 mV to 600 mV		 525 575 625 mV
VHSDSC High-speed disconnect detection threshold Full-/High-speed Signaling Levels(1) (specification refers to differential signal amplitude). (+25.6%),
U_DISCONNECT_THRESHOLD_Px setting 1000, VCM=280 mV to 680 mV		 685 757 846 mV
EQ_UHS USB high-speed data receiver equalization, (measured indirectly through jitter) 240 MHz, U_EQ_Px setting 000 −0.37 0.06 0.57 dB
EQ_UHS USB High-speed data receiver equalization, (measured indirectly through jitter) 240 MHz, U_EQ_Px setting 010 0.62 1.09 1.57 dB
USB OUTPUT LEVELS HS
VHSOH High-speed data signaling high Full-/High-speed Signaling Levels(1), measured single-ended peak voltage per USB 2.0 test measurement spec, U_HS_TX_AMPLITUDE_Px setting 0011, PE disabled, Test load is an ideal 45 Ω to GND on DP and DN 360 400 440 mV
VHSOH High-speed data signaling high Full-/High-speed Signaling Levels(1), measured single ended peak voltage per USB 2.0 test measurement spec, U_HS_TX_AMPLITUDE_Px setting 1100, PE disabled, Test load is an ideal 45 Ω to GND on DP and DN 441 490 539 mV
VHSOD High-speed data signaling swing Measured p-p, 0%, U_HS_TX_AMPLITUDE_Px setting 0011, PE disabled, Test load is an ideal 45 Ω to GND on DP and DN.  720 800 880 mV
VHSOD High-speed data signaling swing Measured p-p, 22.5%, U_HS_TX_AMPLITUDE_Px setting 1100, PE disabled,Test load is an ideal 45 Ω to GND on DP and DN.  882 980 1078 mV
VHSOL High-speed data signaling low, driver is off termination is on (measured single ended) Full-/High-speed Signaling Levels(1), PE disabled, test load is an ideal 45 Ω to GND on DP and DN.  –10 10 mV
VCHIRPJ Host or hub chirp J level (differential voltage)  Full-/High-speed Signaling Levels(1), (PE is disabled. swing setting has no impact but slew rate control has impact), Test load is an ideal 1.5 kΩ pull up on DP. 700 900 1100 mV
VCHIRPK Device chirp K level (differential voltage) Full-/High-speed Signaling Levels(1), (PE is disabled. swing setting has no impact but slew rate control has impact), Test load is an ideal 45 Ω to GND on DP and DN.  -900 -760 -500 mV
VCHIRPK Host or hub Chirp K level (differential voltage) Full-/High-speed Signaling Levels(1), (PE is disabled. swing setting has no impact but slew rate control has impact), Test load is an ideal 1.5 kΩ pull up on DP. -900 -700 -500 mV
U2_TXPE High-speed TX pre-emphasis U_HS_TX_PRE_EMPHASIS_Px setting 000, test load is an ideal 45 Ω to GND on DP and DN.  0.25 0.5 0.75 dB
U2_TXPE High-speed TX pre-emphasis U_HS_TX_PRE_EMPHASIS_Px setting 100, test load is an ideal 45 Ω to GND on DP and DN.  1.7 2.1 2.5 dB
U2_TXPE_UI High-speed TX pre-emphasis width U_HS_TX_PE_WIDTH_Px setting 11 (measured with PE=2.5 dB setting of 101), Test load is an ideal 45 Ω to GND on DP and DN.  0.54 0.65 0.77 UI
eUSB2 TERMINATION
RSRC_HS High-speed transmit source termination impedance High-Speed Tx Electrical Specification(2) 33 40 47 Ω
ΔRSRC_HS High-speed source impedance mismatch High-Speed Tx Electrical Specification(2) 4 Ω
RRCV_DIF High-speed differential receiver termination (repeater) High-Speed Rx Electrical Specification(2) 74 80 86 Ω
RPD Pull-down resistors on eDP/eDN Pull-down(2), active during LS, FS and HS  6 8 10 kΩ
RSRC_LSFS Transmit output impedance Low-Speed /Full-Speed DC Specifications for 1.2 V ± 10%(2), TX output impedance 28 44 59 Ω
CIO_eDx Differential Capacitance  Measured with VNA at 240 MHz, Driver Hi-Z (VCM = 120 mV to 450 mV), measured differentially. 3.9 5.2 pF
eUSB2 FS/LS INPUT LEVELS
VIL Single-ended input low Low-Speed /Full-Speed DC Specifications for 1.2 V ± 10%(2) –0.1 0.399 V
VIL Single-ended input low Low-Speed /Full-Speed DC Specifications for 1.0 V ± 10%(2) −0.1 0.332 V
VIH Single-ended input high Low-Speed /Full-Speed DC Specifications for 1.2 V ± 10%(2) 0.819 1.386 V
VIH Single-ended input high Low-Speed /Full-Speed DC Specifications for 1.0 V ± 10%(2) 0.682 1.1 V
VHYS Receive single-ended hysteresis voltage Low-Speed /Full-Speed DC Specifications for 1.2 V ± 10%(2) 43.2 mV
VHYS Receive single-ended hysteresis voltage Low-Speed /Full-Speed DC Specifications for 1.0 V ± 10%(2) 38 mV
eUSB2 FS/LS OUTPUT LEVELS
VOL Single-ended output low Low-Speed /Full-Speed DC Specifications for 1.2 V ± 10%(2) 0.1 V
VOL Single-ended output low Low-Speed /Full-Speed DC Specifications for 1.0 V ± 10%(2) 0.1 V
VOH Single-ended output high Low-Speed /Full-Speed DC Specifications for 1.2 V ± 10%(2) 0.918 1.32 V
VOH Single-ended output high Low-Speed /Full-Speed DC Specifications for 1.0 V ± 10%(2) 0.765 1.1 V
eUSB2 HS INPUT LEVELS
VRX_CM Receive DC common mode range (low) High-Speed Rx Electrical Specification(2) (normative), low DC common mode RX must tolerate 120 mV
VRX_CM Receive DC common mode range (high) High-Speed Rx Electrical Specification(2) (normative), high DC common mode RX must tolerate 280 mV
VCM_RX_AC Receiver AC common mode (50 MHz–480 MHz) High-Speed Rx Electrical Specification(2) (informative), across the DC common-mode range of 120 mV to 280 mV. (RX capability tested with intentional TX rise/fall time mismatch and prop delay mismatch) -60 60 mV
CRX_CM Receive center-tapped capacitance High-Speed Rx Electrical Specification(2) (informative) 15 50 pF
VEHSSQ Squelch/No-squelch detect threshold  High-Speed Rx Electrical Specification(2), (measured as differential peak voltage at 240 MHz with increasing amplitude)
E_SQUELCH_THRESHOLD_Px setting 100, VCM = 120 mV to 450 mV		 60 81 97 mV
VEHSSQ Squelch/No-squelch detect threshold  High-Speed Rx Electrical Specification(2), (measured as differential peak voltage at 240 MHz with increasing amplitude) E_SQUELCH_THRESHOLD_Px setting 110, VCM = 120 mV to 450 mV 47 67 83 mV
EQ_EHS eUSB2 high-speed data receiver equalization, (measured indirectly through jitter) 240 MHz E_EQ_P1x setting 0000 −0.2 0.34 0.73 dB
eUSB2 HS OUTPUT LEVELS
VEHSOD Transmit differential (terminated) Measured p2p, RL = 80 Ω, E_HS_TX_AMPLITUDE_ Px setting 011, ideal 80 Ω Rx differential termination load 378 420 462 mV
E_TXPE High-speed TX Pre-emphasis E_HS_TX_PRE_EMPHASIS_Px setting 000 −0.2 0 0.2 dB
E_TXPE_UI High-speed TX Pre-emphasis width E_HS_TX_PE_WIDTH_Px setting 00 0.29 0.40 0.59 UI
VE_TX_CM Transmit DC common mode High-Speed Tx Electrical Specification(2) 170 230 mV
(1) USB 2.0 Promoter Group 2000, USB 2.0 Specification USB 2.0 Promoter Group
(2) USB Implementers Forum (2018). Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Rev. 1.2 USB Implementers Forum