JAJSOK4D November   2021  – April 2024 TUSB2E11

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Version Comparison
    1. 4.1 Device Variants
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1  Repeater Mode
      2. 8.4.2  Power Down Mode
      3. 8.4.3  Disabled Mode
      4. 8.4.4  UART Mode
      5. 8.4.5  Auto-Resume ECR
      6. 8.4.6  L2 State Interrupt Modes
      7. 8.4.7  Attach Detect Interrupt Mode
      8. 8.4.8  GPIO Mode
      9. 8.4.9  USB 2.0 High-Speed HOST Disconnect Detection
      10. 8.4.10 Frame Based Low Power Mode
      11. 8.4.11 Battery Charging
    5. 8.5 Manufacturing Test Modes
      1. 8.5.1 USB DP Test Procedure
      2. 8.5.2 USB DM Test Procedure
    6. 8.6 I2C Target Interface
  10. 9 Register Access Protocol (RAP)
  11. 10Register Map
    1. 10.1 TUSB2E11 Registers
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 Power Supply Recommendations
      1. 11.3.1 Power Up Reset
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Example Layout for Application with 1.8V I2C Variant
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Timing Requirements

MINNOMMAXUNIT
I/O TIMING
t_GPIO_PWMinimum GPIO pulse width for interrupt event8µs
RESET TIMING
t_VDD1V8_RAMPRamp time for VDD1V8 to reach minimum 1.62 V2ms
t_VDD3V3_RAMPRamp time for VDD3V3 to reach minimum 3.0 V2ms
t_aRESETBDuration for RESETB to be asserted low to complete reset while powered10us
t_RH_READYTime for the device to be ready to accept RAP and I2C requests and eUSB2 interface to be ready after RESETB is de-asserted or (VDD1V8 and VDD3V3) reach the minimum recommended voltages, whichever is later.3ms
t_RS_READYTime for the device to be ready to accept RAP and I2C requests and eUSB2 interface to be ready after a soft reset through I2C.350µs
REPEATER TIMING
TJ1ETotal additive jitter for eUSB2 to USB 2.0 (output jitter − input jitter) of the repeater.2042ps
TJ1ITotal additive jitter for USB 2.0 to eUSB2 (output jitter − input jitter) of the repeater.1742ps

Te_to_U_DJ1		eUSB2 to USB 2.0 repeater FS jitter to next transition (Per Low-Speed /Full-Speed DC Specifications for 1.2 V ± 10%(1) condition for supply and GND delta). 
−6.0
+6.0		ns

TU_to_e_DJ1		USB 2.0 to eUSB2 repeater FS jitter to next transition (Per Low-Speed /Full-Speed DC Specifications for 1.2 V ± 10%(1) condition for supply and GND delta). 
−3.0
+3.0		ns

TDJ2_e2U		repeater FS paired transition jitter in eUSB2 to USB 2.0 direction (relaxed relative to THDJ2 defined by USB 2.0 ± 1 ns). eUSB2 in 1.2 V signaling mode.
−1.5
+1.5		ns

TDJ2_U2e		repeater FS paired transition jitter in USB 2.0 to eUSB2 direction (relaxed relative to THDJ2 defined by USB 2.0 ± 1 ns). eUSB2 in 1.2 V signaling mode.
−1.5
+1.5		ns
MODE TIMING
TMODE_SWITCHTime needed to change mode from UART bypass mode to and from USB mode 1 µs
TUART_STARTTime needed to start transmitting UART data, post toggling GPIO0 to '0' when in UART strap mode (SCL=1, SDA=0 at power-up) 2ms
I2C (FM+)
tSU_STAStart setup time, SCL (Tr=72 ns – 120 ns), SDA (Tf=6.5 ns – 81.5 ns), 1 MHz FM+260 ns
tSU_STOStop setup time, SCL (Tr=72 ns –120 ns), SDA (Tf=6.5 ns – 81.5 ns), 1 MHz FM+260  ns
tHD_STAStart hold time, SCL (Tr=72 ns – 120 ns), SDA (Tf=6.5 ns – 81.5 ns), 1 MHz FM+260ns
tSU_DATData input or false start/stop, setup time, SCL (Tr=72 ns – 120 ns), SDA (Tf=6.5 ns – 81.5 ns), 1 MHz FM+50ns
tHD_DATData input or False start/stop, hold time, SCL (Tr=72 ns – 120 ns), SDA (Tf=6.5 ns – 81.5 ns), 1 MHz FM+0ns
tVD_DAT, tVD_ACKSDA output delay, SCL (Tr=72 ns – 120 ns), SDA (Tf=6.5 ns – 81.5 ns), 1 MHz FM+20450ns
tHD_DAT_SLData hold time when device is transmitting 6.67ns
tSPGlitch width suppressed5091ns
tBUFBus free time between a STOP and START condition (Master minimum spec that device must tolerate)0.5µs
tLOWLow period for SCL clock (minimum spec that device must tolerate)0.5µs
tHIGHHigh period for SCL clock (minimum spec that device must tolerate)0.26µs
I2C (FM)
tSU_STOStop setup time, SCL (Tr=180 ns – 300 ns), SDA (Tf=6.5 ns – 106.5 ns), 400 kHz FM600  ns
tHD_STAStart hold time, SCL (Tr=180 ns – 300 ns), SDA (Tf=6.5 ns – 106.5 ns), 400 kHz FM600  ns
tSU_STAStart setup time, SCL (Tr=180 ns – 300 ns), SDA (Tf=6.5 ns – 106.5 ns), 400 kHz FM600ns
tSU_DATData input or false start/stop, setup time, SCL (Tr=180 ns – 300 ns), SDA (Tf=6.5 ns – 106.5 ns), 400 kHz FM100ns
tHD_DATData input or false start/stop, hold time, SCL (Tr=180 ns – 300 ns), SDA (Tf=6.5 ns – 106.5 ns), 400 kHz FM0ns
tVD_DAT, tVD_ACKSDA output delay, SCL (Tr=180 ns – 300 ns), SDA (Tf=6.5 ns – 106.5 ns), 400 kHz FM20900ns
tHD_DAT_SLData hold time when device is transmitting13.5ns
tSPGlitch width suppressed5091ns
tBUFBus free time between a STOP and START condition  (minimum spec that device must tolerate)1.3µs
tLOWLow period for SCL clock  (minimum spec that device must tolerate)1.3µs
tHIGHHigh period for SCL clock (Master minimum spec that device must tolerate)0.6µs
I2C (STD)
tSU_STOStop setup time, SCL (Tr=600 ns – 1000 ns), SDA (Tf=6.5 ns – 106.5 ns), 100 kHz STD4  µs
tHD_STAStart hold time, SCL (Tr=600 ns – 1000 ns), SDA (Tf=6.5 ns – 106.5 ns), 100 kHz STD4  µs
tSU_STAStart setup time, SCL (Tr=600 ns – 1000 ns), SDA (Tf=6.5 ns – 106.5 ns), 100 kHz STD4.7µs
tSU_DATData input or false start/stop, setup time, SCL (Tr=600 ns – 1000 ns), SDA (Tf=6.5 ns – 106.5 ns), 100 kHz STD250ns
tHD_DATData input or false start/stop, hold time, SCL (Tr=600 ns – 1000 ns), SDA (Tf=6.5 ns – 106.5 ns), 100 kHz STD5µs
tVD_DAT, tVD_ACKSDA output delay, SCL (Tr=600 ns – 1000 ns), SDA (Tf=6.5 ns – 106.5 ns), 100 kHz STD3.45µs
tHD_DAT_SLData hold time when device is transmitting13.5ns
tSPGlitch width suppressed5091ns
tBUFBus free time between a STOP and START condition (minimum spec that device must tolerate)4.7µs
tLOWLow period for SCL clock (minimum spec that device must tolerate)4.7µs
tHIGHHigh period for SCL clock (minimum spec that device must tolerate)4.0µs
(1) USB Implementers Forum (2018). Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Rev. 1.2 USB Implementers Forum