JAJSN61F May 2015 – March 2022 TUSB320
PRODUCTION DATA
The TUSB320 device supports a VDD in the range of 2.75 V to 5 V. In this particular case, VDD is set to 5 V. A 100-nF capacitor is placed near VDD. If VBUS is guaranteed to be less than 5.5 V, powering the TUSB320 device through a diode can be implemented.
The TUSB320 device is placed into I2C mode by either pulling the ADDR pin high or low. In this case, the ADDR pin is tied to GND which results in a I2C address of 0x60. The SDA and SCL must be pulled up to either 1.8 V or 3.3 V. When pulled up to 3.3 V, the VDD supply must be at least 3 V to keep from back-driving the I2C interface.
The TUSB320 device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320 device into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the EN_N pin is tied to GND.
The INT_N/OUT3 pin is used to notify the PMIC when a change in the TUSB320 I2C registers occurs. This pin is an open drain output and requires an external pullup resistor. The pin should be pulled up to VDD using a 200-kΩ resistor.
The Type-C port mode is determined by the state of the PORT pin. When the PORT pin is pulled low, the TUSB320 device is in UFP mode. The Type-C port mode can also be controlled by the MODE_SELECT register through the I2C interface when the TUSB320 device is in the unattached state.
The VBUS_DET pin must be connected through a 900-kΩ resistor to VBUS on the Type-C that is connected. This large resistor is required to protect the TUSB320 device from large VBUS voltage that is possible in present day systems. This resistor along with internal pulldown keeps the voltage observed by the TUSB320 device in the recommended range.
The USB2 specification requires the bulk capacitance on VBUS based on UFP or DFP. When operating the TUSB320 device in an UFP mode, a bulk capacitance between 1 to 10 µF is required. In this particular case, a 1-µF capacitor was chosen.