JAJSF70B
July 2015 – January 2022
TUSB4020BI-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
概要 (続き)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings (1)
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
3.3-V I/O Electrical Characteristics
7.6
Hub Input Supply Current
7.7
Power-Up Timing Requirements
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Battery Charging Features
8.3.2
USB Power Management
8.3.3
Clock Generation
8.3.4
Power-Up and Reset
8.4
Device Functional Modes
8.4.1
External Configuration Interface
8.5
Programming
8.5.1
One-Time Programmable (OTP) Configuration
8.5.2
I2C EEPROM Operation
8.5.3
SMBus Slave Operation
8.6
Register Maps
8.6.1
Configuration Registers
8.6.1.1
ROM Signature Register (offset = 0h) [reset = 0h]
8.6.1.2
Vendor ID LSB Register (offset = 1h) [reset = 51h]
8.6.1.3
Vendor ID MSB Register (offset = 2h) [reset = 4h]
8.6.1.4
Product ID LSB Register (offset = 3h) [reset = 25h]
8.6.1.5
Product ID MSB Register (offset = 4h) [reset = 80h]
8.6.1.6
Device Configuration Register (offset = 5h) [reset = 1Xh]
8.6.1.7
Battery Charging Support Register (offset = 6h) [reset = 0Xh]
8.6.1.8
Device Removable Configuration Register (offset = 7h) [reset = 0Xh]
8.6.1.9
Port Used Configuration Register (offset = 8h) [reset = 0h]
8.6.1.10
PHY Custom Configuration Register (offset = 9h) [reset = 0h]
8.6.1.11
Device Configuration Register 2 (offset = Ah)
8.6.1.12
UUID Registers (offset = 10h to 1Fh)
8.6.1.13
Language ID LSB Register (offset = 20h)
8.6.1.14
Language ID MSB Register (offset = 21h)
8.6.1.15
Serial Number String Length Register (offset = 22h)
8.6.1.16
Manufacturer String Length Register (offset = 23h)
8.6.1.17
Product String Length Register (offset = 24h)
8.6.1.18
Serial Number Registers (offset = 30h to 4Fh)
8.6.1.19
Manufacturer String Registers (offset = 50h to 8Fh)
8.6.1.20
Product String Registers (offset = 90h to CFh)
8.6.1.21
Additional Feature Configuration Register (offset = F0h)
8.6.1.22
Charging Port Control Register (offset = F2h)
8.6.1.23
Device Status and Command Register (offset = F8h)
9
Application and Implementation
9.1
Application Information
9.1.1
Crystal Requirements
9.1.2
Input Clock Requirements
9.2
Typical Applications
9.2.1
Upstream Port Implementation
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Downstream Port 1 Implementation
9.2.3
Downstream Port 2 Implementation
9.2.4
VBUS Power Switch Implementation
9.2.5
Clock, Reset, and Miscellaneous
9.2.6
Power Implementation
10
Power Supply Recommendations
10.1
Power Supply
10.2
Downstream Port Power
10.3
Ground
11
Layout
11.1
Layout Guidelines
11.1.1
Placement
11.1.2
Package Specific
11.1.3
Differential Pairs
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
サポート・リソース
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PHP|48
MPQF051B
サーマルパッド・メカニカル・データ
PHP|48
PPTD259B
発注情報
jajsf70b_oa
jajsf70b_pm
9.2.1
Upstream Port Implementation
Figure 9-3
Upstream Port Implementation Schematic