JAJSD41E April   2017  – April 2018 TUSB544

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.1
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration in I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Custom Alternate Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 Adjustable VOD Linear Range and DC Gain
      7. 7.4.7 USB3.1 modes
      8. 7.4.8 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 The Following Procedure Should be Followed to Write to TUSB544 I2C Registers:
      2. 7.5.2 The Following Procedure Should be Followed to Read the TUSB544 I2C Registers:
      3. 7.5.3 The Following Procedure Should be Followed for Setting a Starting Sub-Address for I2C Reads:
    6. 7.6 Register Maps
      1. 7.6.1 TUSB544 Registers
        1. 7.6.1.1  GENERAL_4 Register (Offset = Ah) [reset = 1h]
          1. Table 13. GENERAL_4 Register Field Descriptions
        2. 7.6.1.2  GENERAL_5 Register (Offset = Bh) [reset = 0h]
          1. Table 14. GENERAL_5 Register Field Descriptions
        3. 7.6.1.3  GENERAL_6 Register (Offset = Ch) [reset = 0h]
          1. Table 15. GENERAL_6 Register Field Descriptions
        4. 7.6.1.4  DISPLAYPORT_1 Register (Offset = 10h) [reset = 0h]
          1. Table 16. DISPLAYPORT Register Field Descriptions
        5. 7.6.1.5  DISPLAYPORT_2 Register (Offset = 11h) [reset = 0h]
          1. Table 17. DISPLAYPORT_2 Register Field Descriptions
        6. 7.6.1.6  DISPLAYPORT_3 Register (Offset = 12h) [reset = 0h]
          1. Table 18. DISPLAYPORT_3 Register Field Descriptions
        7. 7.6.1.7  DISPLAYPORT_4 Register (Offset = 13h) [reset = 0h]
          1. Table 19. DISPLAYPORT_4 Register Field Descriptions
        8. 7.6.1.8  DISPLAYPORT_5 Register (Offset = 1Bh) [reset = 0h]
          1. Table 20. DISPLAYPORT_5 Register Field Descriptions
        9. 7.6.1.9  USB3.1_1 Register (Offset = 20h) [reset = 0h]
          1. Table 21. USB3.1 Register Field Descriptions
        10. 7.6.1.10 USB3.1_2 Register (Offset = 21h) [reset = 0h]
          1. Table 22. USB3.1_2 Register Field Descriptions
        11. 7.6.1.11 USB3.1_3 Register (Offset = 22h) [reset = 0h]
          1. Table 23. USB3.1_3 Register Field Descriptions
        12. 7.6.1.12 USB3.1_4 Register (Offset = 23h) [reset = 23h]
          1. Table 24. USB3.1_4 Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 only (USB/DP Alternate Mode)
      2. 8.3.2 USB3.1 and 2 lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
      4. 8.3.4 USB 3.1 only (USB/Custom Alternate Mode)
      5. 8.3.5 USB3.1 and 1 Lane of Custom Alt Mode
      6. 8.3.6 USB3.1 and 2 Lane of Custom Alt Mode
      7. 8.3.7 USB3.1 and 4 Lane of Custom Alt Mode
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 AC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
USB Gen 1 Differential Receiver (UTX1P/N, UTX2P/N, DRX1P/N, DRX2P/N)
VRX-DIFF-PP Input differential peak-peak voltage swing linear dynamic range AC-coupled differential peak-to-peak signal measured post CTLE through a reference channel 2000 mVpp
VRX-DC-CM Common-mode voltage bias in the receiver (DC) 0 V
RRX-DIFF-DC Differential input impedance (DC) Present after a GEN1 device is detected on receiver pins 72 120 Ω
RRX-CM-DC Receiver DC common mode impedance Present after a GEN1 device is detected on receiver pins 18 30 Ω
ZRX-HIGH-IMP-DC-POS Common-mode input impedance with termination disabled (DC) Present when no GEN1 device is detected on receiver pins. Measured over the range of 0-500mV with respect to GND. 25 kΩ
VSIGNAL-DET-DIFF-PP Input differential peak-to-peak signal detect assert level At 5 Gbps, no loss at the input, PRBS7 pattern 80 mV
VRX-IDLE-DET-DIFF-PP Input differential peak-to-peak signal detect de-assert Level At 5 Gbps, no loss at the input, PRBS7 pattern 60 mV
VRX-LFPS-DET-DIFF-PP Low frequency periodic signaling (LFPS) detect threshold Below the minimum is squelched. 100 300 mV
VRX-CM-AC-P Peak RX AC common-mode voltage Measured at package pin 150 mV
CRX RX input capacitance to GND At 2.5 GHz 0.5 1 pF
RLRX-DIFF Differential return Loss 50 MHz – 1.25 GHz at 90 Ω –16 dB
2.5 GHz at 90 Ω –14 dB
RLRX-CM Common-mode return loss 50 MHz – 2.5 GHz at 90 Ω –13 dB
EQSS Receiver equalization at maximum setting UEQ[1:0] and
DEQ[1:0]. at 2.5 GHz 		9 dB
USB Gen 1 Differential Transmitter (DTX1P/N, DTX2P/N, URX1P/N, URX2P/N)
VTX-DIFF-PP Transmitter dynamic differential voltage swing range. 1600 mVPP
VTX-RCV-DETECT Amount of voltage change allowed during receiver detection 600 mV
VTX-CM-IDLE-DELTA Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS –600 600 mV
VTX-DC-CM Common-mode voltage bias in the transmitter (DC) 1.75 V
VTX-CM-AC-PP-ACTIVE Tx AC common-mode voltage active Max mismatch from Txp + Txn for both time and amplitude 100 mVPP
VTX-IDLE-DIFF-AC-PP AC electrical idle differential peak-to-peak output voltage At package pins 0 10 mV
VTX-IDLE-DIFF-DC DC electrical idle differential output voltage At package pins after low pass filter to remove AC component 0 14 mV
VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute DC common-mode voltage between U1 and U0 At package pin 200 mV
RTX-DIFF Differential impedance of the driver 75 120 Ω
CAC-COUPLING AC coupling capacitor 75 265 nF
RTX-CM Common-mode impedance of the driver Measured with respect to AC ground over
0–500 mV		 18 30 Ω
ITX-SHORT TX short circuit current TXP/N shorted to GND 67 mA
RLTX-DIFF Differential return loss 50 MHz – 1.25 GHz at 90 Ω –16 dB
2.5 GHz at 90 Ω –13 dB
RLTX-CM Common-mode return loss 50 MHz – 2.5 GHz at 90 Ω –11 dB
AC Characteristics
Crosstalk Differential crosstalk between any signal pairs at 4.05 GHz –30 dB
GLF Low frequency voltage gain at 10 MHz, 200 mVPP < VID
< 2000 mVPP; 0-dB low-frequency gain setting		 –1 0 1 dB
CP1dB-LF Low frequency 1-dB compression point at 10 MHz, 200 mVPP < VID
< 2000 mVPP; VOD linearity setting = 1100mVPP 		1100 mVPP
CP1dB-HF High frequency 1-dB compression point at 4.05 GHz, 200 mVPP < VID
< 2000 mVPP; VOD linearity setting = 1100mVPP 		1200 mVPP
fLF Low frequency cutoff 200 mVPP< VID < 2000 mVPP 25 50 kHz
DJ TX output deterministic jitter 200 mVPP < VID < 2000 mVPP, PRBS7, 5 Gbps 0.05 UIpp
200 mVPP < VID < 2000 mVPP, PRBS7, 8.1 Gbps 0.08 UIpp
TJ TX output total jitter 200 mVPP < VID < 2000 mVPP, PRBS7, 5 Gbps 0.08 UIpp
200 mVPP < VID < 2000 mVPP, PRBS7, 8.1 Gbps 0.135 UIpp
DisplayPort Receiver UTX1P/N, UTX2P/N, URX1P/N, URX2P/N
VID_PP Peak-to-peak input differential dynamic voltage range 2000 mVpp
VIC Input common mode voltage 0 V
CAC AC coupling capacitance 75 200 nF
EQDP Receiver equalizer at maximum setting DEQ[1:0],UEQ[1:0] at 4.05 GHz 9.5 dB
dR Data rate HBR3 8.1 Gbps
Rti Input termination resistance 80 100 120 Ω
DisplayPort Transmitter DTX1P/N, DTX2P/N, DRX1P/N, DRX2P/N
VTX-DIFFPP VOD dynamic range 1500 mV
ITX-SHORT TX short circuit current TXP/N shorted to GND 67 mA
VTX(DC-CM) Common-mode voltage bias in the transmitter (DC) 1.75 V
AUXP/N and SBU1/2
RON Output ON resistance VCC = 3.3 V; VI = 0 to
0.4 V for AUXP;
VI = 2.7 V to 3.6 V for AUXN		 5 10 Ω
ΔRON ON resistance mismatch within pair VCC = 3.3 V; VI = 0 to
0.4V for AUXP;
VI = 2.7V to 3.6V for AUXN		 1 Ω
RON_FLAT ON resistance flatness (RON max – RON min) measured at identical VCC and temperature VCC = 3.3 V; VI = 0 to
0.4V for AUXP;
VI = 2.7V to 3.6 V for AUXN		 2 Ω
VAUXP_DC_CM AUX Channel DC common mode voltage for AUXP and SBU1. VCC = 3.3 V 0 0.4 V
VAUXN_DC_CM AUX Channel DC common mode voltage for AUXN and SBU2 VCC = 3.3 V 2.7 3.6 V
CAUX_ON ON-state capacitance VCC = 3.3V; CTL1 = 1;
VI = 0V or 3.3V		 4 7 pF
CAUX_OFF OFF-state capacitance VCC = 3.3V; CTL1 = 0;
VI = 0V or 3.3V		 3 6 pF