JAJSD41E April 2017 – April 2018 TUSB544
PRODUCTION DATA.
TUSB544 receiver lanes have controls for receiver equalization for upstream and downstream facing ports. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 7 details the gain value for each available combination when TUSB544 is in GPIO mode. These same options are also available per channel and for upstream and downstream facing ports in I2C mode by updating registers URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL.
Downstream Facing Ports | Upstream Facing Port | ||||||
---|---|---|---|---|---|---|---|
DEQ1
pin Level |
DEQ0
pin Level |
EQ GAIN
2.5GHz (dB) |
EQ GAIN
4.05GHz (dB) |
UEQ1
pin Level |
UEQ0
pin Level |
EQ GAIN
2.5GHz (dB) |
EQ GAIN
4.05GHz (dB) |
0 | 0 | -1.0 | -1.4 | 0 | 0 | -2.2 | -3.3 |
0 | R | 0.1 | 0.4 | 0 | R | -1.1 | -1.5 |
0 | F | 1.0 | 1.7 | 0 | F | -0.2 | 0.0 |
0 | 1 | 2.1 | 3.2 | 0 | 1 | 0.9 | 1.4 |
R | 0 | 2.9 | 4.1 | R | 0 | 1.8 | 2.4 |
R | R | 3.8 | 5.2 | R | R | 2.7 | 3.5 |
R | F | 4.6 | 6.1 | R | F | 3.4 | 4.3 |
R | 1 | 5.4 | 6.9 | R | 1 | 4.3 | 5.2 |
F | 0 | 6.1 | 7.7 | F | 0 | 5.0 | 6.0 |
F | R | 6.8 | 8.3 | F | R | 5.7 | 6.6 |
F | F | 7.3 | 8.8 | F | F | 6.2 | 7.2 |
F | 1 | 7.9 | 9.4 | F | 1 | 6.8 | 7.7 |
1 | 0 | 8.4 | 9.8 | 1 | 0 | 7.3 | 8.1 |
1 | R | 8.9 | 10.3 | 1 | R | 7.8 | 8.6 |
1 | F | 9.3 | 10.6 | 1 | F | 8.2 | 9.0 |
1 | 1 | 9.8 | 11.0 | 1 | 1 | 8.7 | 9.4 |